Lines Matching refs:bus
30 * of the bus.
338 static inline void npcm_i2c_select_bank(struct npcm_i2c *bus,
341 u8 i2cctl3 = ioread8(bus->reg + NPCM_I2CCTL3);
347 iowrite8(i2cctl3, bus->reg + NPCM_I2CCTL3);
350 static void npcm_i2c_init_params(struct npcm_i2c *bus)
352 bus->stop_ind = I2C_NO_STATUS_IND;
353 bus->rd_size = 0;
354 bus->wr_size = 0;
355 bus->rd_ind = 0;
356 bus->wr_ind = 0;
357 bus->read_block_use = false;
358 bus->int_time_stamp = 0;
359 bus->PEC_use = false;
360 bus->PEC_mask = 0;
362 if (bus->slave)
363 bus->master_or_slave = I2C_SLAVE;
367 static inline void npcm_i2c_wr_byte(struct npcm_i2c *bus, u8 data)
369 iowrite8(data, bus->reg + NPCM_I2CSDA);
372 static inline u8 npcm_i2c_rd_byte(struct npcm_i2c *bus)
374 return ioread8(bus->reg + NPCM_I2CSDA);
379 struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap);
381 return !!(I2CCTL3_SCL_LVL & ioread8(bus->reg + NPCM_I2CCTL3));
386 struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap);
388 return !!(I2CCTL3_SDA_LVL & ioread8(bus->reg + NPCM_I2CCTL3));
391 static inline u16 npcm_i2c_get_index(struct npcm_i2c *bus)
393 if (bus->operation == I2C_READ_OPER)
394 return bus->rd_ind;
395 if (bus->operation == I2C_WRITE_OPER)
396 return bus->wr_ind;
401 static inline bool npcm_i2c_is_quick(struct npcm_i2c *bus)
403 return bus->wr_size == 0 && bus->rd_size == 0;
406 static void npcm_i2c_disable(struct npcm_i2c *bus)
415 iowrite8(0, bus->reg + npcm_i2caddr[i]);
419 i2cctl2 = ioread8(bus->reg + NPCM_I2CCTL2);
421 iowrite8(i2cctl2, bus->reg + NPCM_I2CCTL2);
423 bus->state = I2C_DISABLE;
426 static void npcm_i2c_enable(struct npcm_i2c *bus)
428 u8 i2cctl2 = ioread8(bus->reg + NPCM_I2CCTL2);
431 iowrite8(i2cctl2, bus->reg + NPCM_I2CCTL2);
432 bus->state = I2C_IDLE;
436 static inline void npcm_i2c_eob_int(struct npcm_i2c *bus, bool enable)
441 val = ioread8(bus->reg + NPCM_I2CCST3);
443 iowrite8(val, bus->reg + NPCM_I2CCST3);
445 val = ioread8(bus->reg + NPCM_I2CCTL1);
451 iowrite8(val, bus->reg + NPCM_I2CCTL1);
454 static inline bool npcm_i2c_tx_fifo_empty(struct npcm_i2c *bus)
458 tx_fifo_sts = ioread8(bus->reg + NPCM_I2CTXF_STS);
460 if ((tx_fifo_sts & bus->data->txf_sts_tx_bytes) == 0)
467 static inline bool npcm_i2c_rx_fifo_full(struct npcm_i2c *bus)
471 rx_fifo_sts = ioread8(bus->reg + NPCM_I2CRXF_STS);
473 if ((rx_fifo_sts & bus->data->rxf_sts_rx_bytes) == 0)
480 static inline void npcm_i2c_clear_fifo_int(struct npcm_i2c *bus)
484 val = ioread8(bus->reg + NPCM_I2CFIF_CTS);
486 iowrite8(val, bus->reg + NPCM_I2CFIF_CTS);
489 static inline void npcm_i2c_clear_tx_fifo(struct npcm_i2c *bus)
493 val = ioread8(bus->reg + NPCM_I2CTXF_STS);
495 iowrite8(val, bus->reg + NPCM_I2CTXF_STS);
498 static inline void npcm_i2c_clear_rx_fifo(struct npcm_i2c *bus)
502 val = ioread8(bus->reg + NPCM_I2CRXF_STS);
504 iowrite8(val, bus->reg + NPCM_I2CRXF_STS);
507 static void npcm_i2c_int_enable(struct npcm_i2c *bus, bool enable)
511 val = ioread8(bus->reg + NPCM_I2CCTL1);
517 iowrite8(val, bus->reg + NPCM_I2CCTL1);
520 static inline void npcm_i2c_master_start(struct npcm_i2c *bus)
524 val = ioread8(bus->reg + NPCM_I2CCTL1);
527 iowrite8(val, bus->reg + NPCM_I2CCTL1);
530 static inline void npcm_i2c_master_stop(struct npcm_i2c *bus)
540 val = ioread8(bus->reg + NPCM_I2CCTL1);
543 iowrite8(val, bus->reg + NPCM_I2CCTL1);
545 if (!bus->fifo_use)
548 npcm_i2c_select_bank(bus, I2C_BANK_1);
550 if (bus->operation == I2C_READ_OPER)
551 npcm_i2c_clear_rx_fifo(bus);
553 npcm_i2c_clear_tx_fifo(bus);
554 npcm_i2c_clear_fifo_int(bus);
555 iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
558 static inline void npcm_i2c_stall_after_start(struct npcm_i2c *bus, bool stall)
562 val = ioread8(bus->reg + NPCM_I2CCTL1);
568 iowrite8(val, bus->reg + NPCM_I2CCTL1);
571 static inline void npcm_i2c_nack(struct npcm_i2c *bus)
575 val = ioread8(bus->reg + NPCM_I2CCTL1);
578 iowrite8(val, bus->reg + NPCM_I2CCTL1);
581 static inline void npcm_i2c_clear_master_status(struct npcm_i2c *bus)
587 iowrite8(val, bus->reg + NPCM_I2CST);
591 static void npcm_i2c_slave_int_enable(struct npcm_i2c *bus, bool enable)
596 i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1);
602 iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1);
605 static int npcm_i2c_slave_enable(struct npcm_i2c *bus, enum i2c_addr addr_type,
614 i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1);
619 iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1);
622 i2cctl3 = ioread8(bus->reg + NPCM_I2CCTL3);
627 iowrite8(i2cctl3, bus->reg + NPCM_I2CCTL3);
631 dev_err(bus->dev, "try to enable more than 2 SA not supported\n");
637 iowrite8(sa_reg, bus->reg + npcm_i2caddr[addr_type]);
638 npcm_i2c_slave_int_enable(bus, enable);
644 static void npcm_i2c_reset(struct npcm_i2c *bus)
655 i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1);
657 npcm_i2c_disable(bus);
658 npcm_i2c_enable(bus);
662 iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1);
665 iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST);
666 iowrite8(0xFF, bus->reg + NPCM_I2CST);
669 npcm_i2c_eob_int(bus, false);
672 iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS);
675 if (bus->slave) {
676 addr = bus->slave->addr;
677 npcm_i2c_slave_enable(bus, I2C_SLAVE_ADDR1, addr, true);
682 npcm_i2c_clear_master_status(bus);
684 bus->state = I2C_IDLE;
687 static inline bool npcm_i2c_is_master(struct npcm_i2c *bus)
689 return !!FIELD_GET(NPCM_I2CST_MASTER, ioread8(bus->reg + NPCM_I2CST));
692 static void npcm_i2c_callback(struct npcm_i2c *bus,
699 msgs = bus->msgs;
700 msgs_num = bus->msgs_num;
708 if (completion_done(&bus->cmd_complete))
713 bus->cmd_err = bus->msgs_num;
714 if (bus->tx_complete_cnt < ULLONG_MAX)
715 bus->tx_complete_cnt++;
719 if (bus->msgs) {
730 bus->cmd_err = -ENXIO;
735 bus->cmd_err = -EAGAIN;
745 bus->operation = I2C_NO_OPER;
747 if (bus->slave)
748 bus->master_or_slave = I2C_SLAVE;
751 complete(&bus->cmd_complete);
754 static u8 npcm_i2c_fifo_usage(struct npcm_i2c *bus)
756 if (bus->operation == I2C_WRITE_OPER)
757 return (bus->data->txf_sts_tx_bytes &
758 ioread8(bus->reg + NPCM_I2CTXF_STS));
759 if (bus->operation == I2C_READ_OPER)
760 return (bus->data->rxf_sts_rx_bytes &
761 ioread8(bus->reg + NPCM_I2CRXF_STS));
765 static void npcm_i2c_write_to_fifo_master(struct npcm_i2c *bus, u16 max_bytes)
773 size_free_fifo = bus->data->fifo_size - npcm_i2c_fifo_usage(bus);
775 if (bus->wr_ind < bus->wr_size)
776 npcm_i2c_wr_byte(bus, bus->wr_buf[bus->wr_ind++]);
778 npcm_i2c_wr_byte(bus, 0xFF);
779 size_free_fifo = bus->data->fifo_size - npcm_i2c_fifo_usage(bus);
788 static void npcm_i2c_set_fifo(struct npcm_i2c *bus, int nread, int nwrite)
792 if (!bus->fifo_use)
794 npcm_i2c_select_bank(bus, I2C_BANK_1);
795 npcm_i2c_clear_tx_fifo(bus);
796 npcm_i2c_clear_rx_fifo(bus);
800 rxf_ctl = min_t(int, nread, bus->data->fifo_size);
803 if (nread <= bus->data->fifo_size)
804 rxf_ctl |= bus->data->rxf_ctl_last_pec;
811 if (bus->rd_ind == 0 && bus->read_block_use) {
817 iowrite8(rxf_ctl, bus->reg + NPCM_I2CRXF_CTL);
822 if (nwrite > bus->data->fifo_size)
824 iowrite8(bus->data->fifo_size, bus->reg + NPCM_I2CTXF_CTL);
826 iowrite8(nwrite, bus->reg + NPCM_I2CTXF_CTL);
828 npcm_i2c_clear_tx_fifo(bus);
832 static void npcm_i2c_read_fifo(struct npcm_i2c *bus, u8 bytes_in_fifo)
837 data = npcm_i2c_rd_byte(bus);
838 if (bus->rd_ind < bus->rd_size)
839 bus->rd_buf[bus->rd_ind++] = data;
843 static void npcm_i2c_master_abort(struct npcm_i2c *bus)
846 if (!npcm_i2c_is_master(bus))
849 npcm_i2c_eob_int(bus, true);
850 npcm_i2c_master_stop(bus);
851 npcm_i2c_clear_master_status(bus);
855 static u8 npcm_i2c_get_slave_addr(struct npcm_i2c *bus, enum i2c_addr addr_type)
860 dev_err(bus->dev, "get slave: try to use more than 2 SA not supported\n");
862 slave_add = ioread8(bus->reg + npcm_i2caddr[(int)addr_type]);
867 static int npcm_i2c_remove_slave_addr(struct npcm_i2c *bus, u8 slave_add)
875 if (ioread8(bus->reg + npcm_i2caddr[i]) == slave_add)
876 iowrite8(0, bus->reg + npcm_i2caddr[i]);
882 static void npcm_i2c_write_fifo_slave(struct npcm_i2c *bus, u16 max_bytes)
888 npcm_i2c_clear_fifo_int(bus);
889 npcm_i2c_clear_tx_fifo(bus);
890 iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
891 while (max_bytes-- && bus->data->fifo_size != npcm_i2c_fifo_usage(bus)) {
892 if (bus->slv_wr_size <= 0)
894 bus->slv_wr_ind = bus->slv_wr_ind & (bus->data->fifo_size - 1);
895 npcm_i2c_wr_byte(bus, bus->slv_wr_buf[bus->slv_wr_ind]);
896 bus->slv_wr_ind++;
897 bus->slv_wr_ind = bus->slv_wr_ind & (bus->data->fifo_size - 1);
898 bus->slv_wr_size--;
902 static void npcm_i2c_read_fifo_slave(struct npcm_i2c *bus, u8 bytes_in_fifo)
906 if (!bus->slave)
910 data = npcm_i2c_rd_byte(bus);
912 bus->slv_rd_ind = bus->slv_rd_ind & (bus->data->fifo_size - 1);
913 bus->slv_rd_buf[bus->slv_rd_ind] = data;
914 bus->slv_rd_ind++;
917 if (bus->slv_rd_ind == 1 && bus->read_block_use)
918 bus->slv_rd_size = data + bus->PEC_use + 1;
922 static int npcm_i2c_slave_get_wr_buf(struct npcm_i2c *bus)
927 int ret = bus->slv_wr_ind;
930 for (i = 0; i < bus->data->fifo_size; i++) {
931 if (bus->slv_wr_size >= bus->data->fifo_size)
933 if (bus->state == I2C_SLAVE_MATCH) {
934 i2c_slave_event(bus->slave, I2C_SLAVE_READ_REQUESTED, &value);
935 bus->state = I2C_OPER_STARTED;
937 i2c_slave_event(bus->slave, I2C_SLAVE_READ_PROCESSED, &value);
939 ind = (bus->slv_wr_ind + bus->slv_wr_size) & (bus->data->fifo_size - 1);
940 bus->slv_wr_buf[ind] = value;
941 bus->slv_wr_size++;
943 return bus->data->fifo_size - ret;
946 static void npcm_i2c_slave_send_rd_buf(struct npcm_i2c *bus)
950 for (i = 0; i < bus->slv_rd_ind; i++)
951 i2c_slave_event(bus->slave, I2C_SLAVE_WRITE_RECEIVED,
952 &bus->slv_rd_buf[i]);
957 if (bus->slv_rd_ind) {
958 bus->slv_wr_size = 0;
959 bus->slv_wr_ind = 0;
962 bus->slv_rd_ind = 0;
963 bus->slv_rd_size = bus->adap.quirks->max_read_len;
965 npcm_i2c_clear_fifo_int(bus);
966 npcm_i2c_clear_rx_fifo(bus);
969 static void npcm_i2c_slave_receive(struct npcm_i2c *bus, u16 nread,
972 bus->state = I2C_OPER_STARTED;
973 bus->operation = I2C_READ_OPER;
974 bus->slv_rd_size = nread;
975 bus->slv_rd_ind = 0;
977 iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
978 iowrite8(bus->data->fifo_size, bus->reg + NPCM_I2CRXF_CTL);
979 npcm_i2c_clear_tx_fifo(bus);
980 npcm_i2c_clear_rx_fifo(bus);
983 static void npcm_i2c_slave_xmit(struct npcm_i2c *bus, u16 nwrite,
989 bus->operation = I2C_WRITE_OPER;
992 npcm_i2c_slave_get_wr_buf(bus);
993 npcm_i2c_write_fifo_slave(bus, nwrite);
1001 * to the FIFO and onward to the bus.
1002 * NACK on read will be once reached to bus->adap->quirks->max_read_len.
1007 static void npcm_i2c_slave_wr_buf_sync(struct npcm_i2c *bus)
1011 left_in_fifo = bus->data->txf_sts_tx_bytes &
1012 ioread8(bus->reg + NPCM_I2CTXF_STS);
1015 if (left_in_fifo >= bus->data->fifo_size ||
1016 bus->slv_wr_size >= bus->data->fifo_size)
1020 bus->slv_wr_ind = bus->slv_wr_ind - left_in_fifo;
1021 bus->slv_wr_size = bus->slv_wr_size + left_in_fifo;
1023 if (bus->slv_wr_ind < 0)
1024 bus->slv_wr_ind += bus->data->fifo_size;
1027 static void npcm_i2c_slave_rd_wr(struct npcm_i2c *bus)
1029 if (NPCM_I2CST_XMIT & ioread8(bus->reg + NPCM_I2CST)) {
1034 bus->operation = I2C_WRITE_OPER;
1035 npcm_i2c_slave_xmit(bus, bus->adap.quirks->max_write_len,
1036 bus->slv_wr_buf);
1044 bus->operation = I2C_READ_OPER;
1045 npcm_i2c_read_fifo_slave(bus, npcm_i2c_fifo_usage(bus));
1046 bus->stop_ind = I2C_SLAVE_RCV_IND;
1047 npcm_i2c_slave_send_rd_buf(bus);
1048 npcm_i2c_slave_receive(bus, bus->adap.quirks->max_read_len,
1049 bus->slv_rd_buf);
1053 static irqreturn_t npcm_i2c_int_slave_handler(struct npcm_i2c *bus)
1057 u8 i2cst = ioread8(bus->reg + NPCM_I2CST);
1061 bus->stop_ind = I2C_NACK_IND;
1062 npcm_i2c_slave_wr_buf_sync(bus);
1063 if (bus->fifo_use)
1066 bus->reg + NPCM_I2CFIF_CTS);
1069 bus->stop_ind = I2C_NO_STATUS_IND;
1070 bus->operation = I2C_NO_OPER;
1071 bus->own_slave_addr = 0xFF;
1077 iowrite8(NPCM_I2CST_NEGACK, bus->reg + NPCM_I2CST);
1085 * Check whether bus arbitration or Start or Stop during data
1086 * xfer bus arbitration problem should not result in recovery
1088 bus->stop_ind = I2C_BUS_ERR_IND;
1090 /* wait for bus busy before clear fifo */
1091 iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS);
1093 bus->state = I2C_IDLE;
1099 if (completion_done(&bus->cmd_complete) == false) {
1100 bus->cmd_err = -EIO;
1101 complete(&bus->cmd_complete);
1103 bus->own_slave_addr = 0xFF;
1104 iowrite8(NPCM_I2CST_BER, bus->reg + NPCM_I2CST);
1110 u8 bytes_in_fifo = npcm_i2c_fifo_usage(bus);
1112 bus->stop_ind = I2C_SLAVE_DONE_IND;
1114 if (bus->operation == I2C_READ_OPER)
1115 npcm_i2c_read_fifo_slave(bus, bytes_in_fifo);
1118 npcm_i2c_slave_send_rd_buf(bus);
1121 bus->stop_ind = I2C_NO_STATUS_IND;
1128 bus->operation = I2C_NO_OPER;
1129 bus->own_slave_addr = 0xFF;
1130 i2c_slave_event(bus->slave, I2C_SLAVE_STOP, 0);
1131 iowrite8(NPCM_I2CST_SLVSTP, bus->reg + NPCM_I2CST);
1132 if (bus->fifo_use) {
1133 npcm_i2c_clear_fifo_int(bus);
1134 npcm_i2c_clear_rx_fifo(bus);
1135 npcm_i2c_clear_tx_fifo(bus);
1138 bus->reg + NPCM_I2CFIF_CTS);
1140 bus->state = I2C_IDLE;
1145 if (bus->fifo_use && FIELD_GET(NPCM_I2CFIF_CTS_SLVRSTR,
1146 ioread8(bus->reg + NPCM_I2CFIF_CTS))) {
1147 bus->stop_ind = I2C_SLAVE_RESTART_IND;
1148 bus->master_or_slave = I2C_SLAVE;
1149 if (bus->operation == I2C_READ_OPER)
1150 npcm_i2c_read_fifo_slave(bus, npcm_i2c_fifo_usage(bus));
1151 bus->operation = I2C_WRITE_OPER;
1152 iowrite8(0, bus->reg + NPCM_I2CRXF_CTL);
1155 iowrite8(val, bus->reg + NPCM_I2CFIF_CTS);
1156 npcm_i2c_slave_rd_wr(bus);
1165 bus->master_or_slave = I2C_SLAVE;
1166 npcm_i2c_clear_fifo_int(bus);
1167 npcm_i2c_clear_rx_fifo(bus);
1168 npcm_i2c_clear_tx_fifo(bus);
1169 iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
1170 iowrite8(bus->data->fifo_size, bus->reg + NPCM_I2CRXF_CTL);
1172 bus->operation = I2C_WRITE_OPER;
1174 i2c_slave_event(bus->slave, I2C_SLAVE_WRITE_REQUESTED,
1176 bus->operation = I2C_READ_OPER;
1178 if (bus->own_slave_addr == 0xFF) {
1180 val = ioread8(bus->reg + NPCM_I2CCST);
1187 i2ccst3 = ioread8(bus->reg + NPCM_I2CCST3);
1188 i2ccst2 = ioread8(bus->reg + NPCM_I2CCST2);
1199 addr = npcm_i2c_get_slave_addr(bus, eaddr);
1201 bus->own_slave_addr = addr;
1202 if (bus->PEC_mask & BIT(info))
1203 bus->PEC_use = true;
1205 bus->PEC_use = false;
1208 bus->own_slave_addr = 0;
1210 bus->own_slave_addr = 0x61;
1221 if ((bus->state == I2C_OPER_STARTED &&
1222 bus->operation == I2C_READ_OPER &&
1223 bus->stop_ind == I2C_SLAVE_XMIT_IND) ||
1224 bus->stop_ind == I2C_SLAVE_RCV_IND) {
1226 bus->stop_ind = I2C_SLAVE_RESTART_IND;
1231 bus->stop_ind = I2C_SLAVE_XMIT_IND;
1233 bus->stop_ind = I2C_SLAVE_RCV_IND;
1234 bus->state = I2C_SLAVE_MATCH;
1235 npcm_i2c_slave_rd_wr(bus);
1236 iowrite8(NPCM_I2CST_NMATCH, bus->reg + NPCM_I2CST);
1242 (bus->fifo_use &&
1243 (npcm_i2c_tx_fifo_empty(bus) || npcm_i2c_rx_fifo_full(bus)))) {
1244 npcm_i2c_slave_rd_wr(bus);
1245 iowrite8(NPCM_I2CST_SDAST, bus->reg + NPCM_I2CST);
1254 npcm_i2c_eob_int(bus, false);
1255 npcm_i2c_clear_master_status(bus);
1264 struct npcm_i2c *bus = i2c_get_adapdata(client->adapter);
1266 bus->slave = client;
1268 if (!bus->slave)
1274 spin_lock_irqsave(&bus->lock, lock_flags);
1276 npcm_i2c_init_params(bus);
1277 bus->slv_rd_size = 0;
1278 bus->slv_wr_size = 0;
1279 bus->slv_rd_ind = 0;
1280 bus->slv_wr_ind = 0;
1282 bus->PEC_use = true;
1284 dev_info(bus->dev, "i2c%d register slave SA=0x%x, PEC=%d\n", bus->num,
1285 client->addr, bus->PEC_use);
1287 npcm_i2c_slave_enable(bus, I2C_SLAVE_ADDR1, client->addr, true);
1288 npcm_i2c_clear_fifo_int(bus);
1289 npcm_i2c_clear_rx_fifo(bus);
1290 npcm_i2c_clear_tx_fifo(bus);
1291 npcm_i2c_slave_int_enable(bus, true);
1293 spin_unlock_irqrestore(&bus->lock, lock_flags);
1299 struct npcm_i2c *bus = client->adapter->algo_data;
1302 spin_lock_irqsave(&bus->lock, lock_flags);
1303 if (!bus->slave) {
1304 spin_unlock_irqrestore(&bus->lock, lock_flags);
1307 npcm_i2c_slave_int_enable(bus, false);
1308 npcm_i2c_remove_slave_addr(bus, client->addr);
1309 bus->slave = NULL;
1310 spin_unlock_irqrestore(&bus->lock, lock_flags);
1315 static void npcm_i2c_master_fifo_read(struct npcm_i2c *bus)
1321 fifo_bytes = npcm_i2c_fifo_usage(bus);
1322 rcount = bus->rd_size - bus->rd_ind;
1331 if (rcount < (2 * bus->data->fifo_size) && rcount > bus->data->fifo_size)
1332 fifo_bytes = rcount - bus->data->fifo_size;
1336 bus->state = I2C_STOP_PENDING;
1337 bus->stop_ind = ind;
1338 npcm_i2c_eob_int(bus, true);
1340 npcm_i2c_master_stop(bus);
1341 npcm_i2c_read_fifo(bus, fifo_bytes);
1343 npcm_i2c_read_fifo(bus, fifo_bytes);
1344 rcount = bus->rd_size - bus->rd_ind;
1345 npcm_i2c_set_fifo(bus, rcount, -1);
1349 static void npcm_i2c_irq_master_handler_write(struct npcm_i2c *bus)
1353 if (bus->fifo_use)
1354 npcm_i2c_clear_tx_fifo(bus); /* clear the TX fifo status bit */
1357 if (bus->wr_ind == bus->wr_size) {
1358 if (bus->fifo_use && npcm_i2c_fifo_usage(bus) > 0)
1368 if (bus->rd_size == 0) {
1370 npcm_i2c_eob_int(bus, true);
1371 bus->state = I2C_STOP_PENDING;
1372 bus->stop_ind = I2C_MASTER_DONE_IND;
1373 npcm_i2c_master_stop(bus);
1375 npcm_i2c_wr_byte(bus, 0xFF);
1379 npcm_i2c_set_fifo(bus, bus->rd_size, -1);
1381 npcm_i2c_master_start(bus);
1389 if (bus->rd_size == 1)
1390 npcm_i2c_stall_after_start(bus, true);
1393 bus->operation = I2C_READ_OPER;
1395 npcm_i2c_wr_byte(bus, bus->dest_addr | 0x1);
1399 if (!bus->fifo_use || bus->wr_size == 1) {
1400 npcm_i2c_wr_byte(bus, bus->wr_buf[bus->wr_ind++]);
1402 wcount = bus->wr_size - bus->wr_ind;
1403 npcm_i2c_set_fifo(bus, -1, wcount);
1405 npcm_i2c_write_to_fifo_master(bus, wcount);
1410 static void npcm_i2c_irq_master_handler_read(struct npcm_i2c *bus)
1416 block_extra_bytes_size = bus->read_block_use + bus->PEC_use;
1422 if (bus->rd_ind == 0) { /* first byte handling: */
1423 if (bus->read_block_use) {
1425 data = npcm_i2c_rd_byte(bus);
1427 bus->rd_size = data + block_extra_bytes_size;
1428 bus->rd_buf[bus->rd_ind++] = data;
1431 if (bus->fifo_use) {
1432 data = ioread8(bus->reg + NPCM_I2CFIF_CTS);
1434 iowrite8(data, bus->reg + NPCM_I2CFIF_CTS);
1437 npcm_i2c_set_fifo(bus, bus->rd_size - 1, -1);
1438 npcm_i2c_stall_after_start(bus, false);
1440 npcm_i2c_clear_tx_fifo(bus);
1441 npcm_i2c_master_fifo_read(bus);
1444 if (bus->rd_size == block_extra_bytes_size &&
1445 bus->read_block_use) {
1446 bus->state = I2C_STOP_PENDING;
1447 bus->stop_ind = I2C_BLOCK_BYTES_ERR_IND;
1448 bus->cmd_err = -EIO;
1449 npcm_i2c_eob_int(bus, true);
1450 npcm_i2c_master_stop(bus);
1451 npcm_i2c_read_fifo(bus, npcm_i2c_fifo_usage(bus));
1453 npcm_i2c_master_fifo_read(bus);
1458 static void npcm_i2c_irq_handle_nmatch(struct npcm_i2c *bus)
1460 iowrite8(NPCM_I2CST_NMATCH, bus->reg + NPCM_I2CST);
1461 npcm_i2c_nack(bus);
1462 bus->stop_ind = I2C_BUS_ERR_IND;
1463 npcm_i2c_callback(bus, bus->stop_ind, npcm_i2c_get_index(bus));
1467 static void npcm_i2c_irq_handle_nack(struct npcm_i2c *bus)
1471 if (bus->nack_cnt < ULLONG_MAX)
1472 bus->nack_cnt++;
1474 if (bus->fifo_use) {
1479 if (bus->operation == I2C_WRITE_OPER)
1480 bus->wr_ind -= npcm_i2c_fifo_usage(bus);
1483 iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS);
1487 bus->stop_ind = I2C_NACK_IND;
1489 if (npcm_i2c_is_master(bus)) {
1491 npcm_i2c_eob_int(bus, false);
1492 npcm_i2c_master_stop(bus);
1495 npcm_i2c_rd_byte(bus);
1498 * The bus is released from stall only after the SW clears
1501 npcm_i2c_clear_master_status(bus);
1502 readx_poll_timeout_atomic(ioread8, bus->reg + NPCM_I2CCST, val,
1504 /* Verify no status bits are still set after bus is released */
1505 npcm_i2c_clear_master_status(bus);
1507 bus->state = I2C_IDLE;
1511 * In such case, the bus is released from stall only after the
1514 npcm_i2c_callback(bus, bus->stop_ind, bus->wr_ind);
1518 static void npcm_i2c_irq_handle_ber(struct npcm_i2c *bus)
1520 if (bus->ber_cnt < ULLONG_MAX)
1521 bus->ber_cnt++;
1522 bus->stop_ind = I2C_BUS_ERR_IND;
1523 if (npcm_i2c_is_master(bus)) {
1524 npcm_i2c_master_abort(bus);
1526 npcm_i2c_clear_master_status(bus);
1529 iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST);
1531 bus->cmd_err = -EAGAIN;
1532 npcm_i2c_callback(bus, bus->stop_ind, npcm_i2c_get_index(bus));
1534 bus->state = I2C_IDLE;
1538 static void npcm_i2c_irq_handle_eob(struct npcm_i2c *bus)
1540 npcm_i2c_eob_int(bus, false);
1541 bus->state = I2C_IDLE;
1542 npcm_i2c_callback(bus, bus->stop_ind, bus->rd_ind);
1546 static void npcm_i2c_irq_handle_stall_after_start(struct npcm_i2c *bus)
1548 if (npcm_i2c_is_quick(bus)) {
1549 bus->state = I2C_STOP_PENDING;
1550 bus->stop_ind = I2C_MASTER_DONE_IND;
1551 npcm_i2c_eob_int(bus, true);
1552 npcm_i2c_master_stop(bus);
1553 } else if ((bus->rd_size == 1) && !bus->read_block_use) {
1558 npcm_i2c_nack(bus);
1562 npcm_i2c_stall_after_start(bus, false);
1565 iowrite8(NPCM_I2CST_STASTR, bus->reg + NPCM_I2CST);
1569 static void npcm_i2c_irq_handle_sda(struct npcm_i2c *bus, u8 i2cst)
1573 if (!npcm_i2c_is_master(bus))
1576 if (bus->state == I2C_IDLE) {
1577 bus->stop_ind = I2C_WAKE_UP_IND;
1579 if (npcm_i2c_is_quick(bus) || bus->read_block_use)
1584 npcm_i2c_stall_after_start(bus, true);
1586 npcm_i2c_stall_after_start(bus, false);
1594 if (bus->wr_size == 0 && bus->rd_size == 1)
1595 npcm_i2c_stall_after_start(bus, true);
1600 npcm_i2c_select_bank(bus, I2C_BANK_1);
1602 fif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS);
1607 iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS);
1611 iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS);
1620 if (bus->wr_size)
1621 npcm_i2c_set_fifo(bus, -1, bus->wr_size);
1623 npcm_i2c_set_fifo(bus, bus->rd_size, -1);
1625 bus->state = I2C_OPER_STARTED;
1627 if (npcm_i2c_is_quick(bus) || bus->wr_size)
1628 npcm_i2c_wr_byte(bus, bus->dest_addr);
1630 npcm_i2c_wr_byte(bus, bus->dest_addr | BIT(0));
1634 bus->operation = I2C_WRITE_OPER;
1635 npcm_i2c_irq_master_handler_write(bus);
1637 bus->operation = I2C_READ_OPER;
1638 npcm_i2c_irq_master_handler_read(bus);
1643 static int npcm_i2c_int_master_handler(struct npcm_i2c *bus)
1648 i2cst = ioread8(bus->reg + NPCM_I2CST);
1651 npcm_i2c_irq_handle_nmatch(bus);
1656 npcm_i2c_irq_handle_nack(bus);
1662 npcm_i2c_irq_handle_ber(bus);
1668 ioread8(bus->reg + NPCM_I2CCTL1)) == 1) &&
1670 ioread8(bus->reg + NPCM_I2CCST3)))) {
1671 npcm_i2c_irq_handle_eob(bus);
1677 npcm_i2c_irq_handle_stall_after_start(bus);
1683 (bus->fifo_use &&
1684 (npcm_i2c_tx_fifo_empty(bus) || npcm_i2c_rx_fifo_full(bus)))) {
1685 npcm_i2c_irq_handle_sda(bus, i2cst);
1699 struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap);
1704 dev_dbg(bus->dev, "bus%d-0x%x recovery skipped, bus not stuck",
1705 bus->num, bus->dest_addr);
1706 npcm_i2c_reset(bus);
1710 npcm_i2c_int_enable(bus, false);
1711 npcm_i2c_disable(bus);
1712 npcm_i2c_enable(bus);
1713 iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST);
1714 npcm_i2c_clear_tx_fifo(bus);
1715 npcm_i2c_clear_rx_fifo(bus);
1716 iowrite8(0, bus->reg + NPCM_I2CRXF_CTL);
1717 iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
1718 npcm_i2c_stall_after_start(bus, false);
1721 npcm_i2c_select_bank(bus, I2C_BANK_1);
1724 fif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS);
1727 iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS);
1728 npcm_i2c_set_fifo(bus, -1, 0);
1733 iowrite8(NPCM_I2CCST_TGSCL, bus->reg + NPCM_I2CCST);
1745 npcm_i2c_wr_byte(bus, bus->dest_addr);
1746 npcm_i2c_master_start(bus);
1751 if (npcm_i2c_is_master(bus) > 0) {
1753 npcm_i2c_master_stop(bus);
1757 npcm_i2c_reset(bus);
1758 npcm_i2c_int_enable(bus, true);
1765 if (bus->rec_fail_cnt < ULLONG_MAX)
1766 bus->rec_fail_cnt++;
1768 if (bus->rec_succ_cnt < ULLONG_MAX)
1769 bus->rec_succ_cnt++;
1777 struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap);
1778 struct i2c_bus_recovery_info *rinfo = &bus->rinfo;
1801 * and bus frequency.
1802 * 100kHz bus requires tSCL = 4 * SCLFRQ * tCLK. LT and HT are symmetric.
1803 * 400kHz bus requires asymmetric HT and LT. A different equation is recommended
1807 static int npcm_i2c_init_clk(struct npcm_i2c *bus, u32 bus_freq_hz)
1818 src_clk_khz = bus->apb_clk / 1000;
1820 bus->bus_freq = bus_freq_hz;
1901 bus->reg + NPCM_I2CCTL2);
1905 bus->reg + NPCM_I2CCTL3);
1908 npcm_i2c_select_bank(bus, I2C_BANK_0);
1916 iowrite8(k1 / 2, bus->reg + NPCM_I2CSCLLT);
1917 iowrite8(k2 / 2, bus->reg + NPCM_I2CSCLHT);
1919 iowrite8(dbnct, bus->reg + NPCM_I2CCTL5);
1922 iowrite8(hldt, bus->reg + NPCM_I2CCTL4);
1925 npcm_i2c_select_bank(bus, I2C_BANK_1);
1930 static int npcm_i2c_init_module(struct npcm_i2c *bus, enum i2c_mode mode,
1937 if ((bus->state != I2C_DISABLE && bus->state != I2C_IDLE) ||
1941 npcm_i2c_int_enable(bus, false);
1942 npcm_i2c_disable(bus);
1945 if (FIELD_GET(I2C_VER_FIFO_EN, ioread8(bus->reg + I2C_VER))) {
1946 bus->fifo_use = true;
1947 npcm_i2c_select_bank(bus, I2C_BANK_0);
1948 val = ioread8(bus->reg + NPCM_I2CFIF_CTL);
1950 iowrite8(val, bus->reg + NPCM_I2CFIF_CTL);
1951 npcm_i2c_select_bank(bus, I2C_BANK_1);
1953 bus->fifo_use = false;
1957 ret = npcm_i2c_init_clk(bus, bus_freq_hz);
1959 dev_err(bus->dev, "npcm_i2c_init_clk failed\n");
1964 npcm_i2c_enable(bus);
1965 bus->state = I2C_IDLE;
1966 val = ioread8(bus->reg + NPCM_I2CCTL1);
1968 iowrite8(val, bus->reg + NPCM_I2CCTL1);
1970 npcm_i2c_reset(bus);
1973 if ((npcm_i2c_get_SDA(&bus->adap) == 0) || (npcm_i2c_get_SCL(&bus->adap) == 0)) {
1974 dev_err(bus->dev, "I2C%d init fail: lines are low\n", bus->num);
1975 dev_err(bus->dev, "SDA=%d SCL=%d\n", npcm_i2c_get_SDA(&bus->adap),
1976 npcm_i2c_get_SCL(&bus->adap));
1980 npcm_i2c_int_enable(bus, true);
1984 static int __npcm_i2c_init(struct npcm_i2c *bus, struct platform_device *pdev)
1990 bus->state = I2C_DISABLE;
1991 bus->master_or_slave = I2C_SLAVE;
1992 bus->int_time_stamp = 0;
1994 bus->slave = NULL;
2004 ret = npcm_i2c_init_module(bus, I2C_MASTER, clk_freq_hz);
2015 struct npcm_i2c *bus = dev_id;
2017 if (npcm_i2c_is_master(bus))
2018 bus->master_or_slave = I2C_MASTER;
2020 if (bus->master_or_slave == I2C_MASTER) {
2021 bus->int_time_stamp = jiffies;
2022 if (!npcm_i2c_int_master_handler(bus))
2026 if (bus->slave) {
2027 bus->master_or_slave = I2C_SLAVE;
2028 if (npcm_i2c_int_slave_handler(bus))
2033 npcm_i2c_clear_master_status(bus);
2038 static bool npcm_i2c_master_start_xmit(struct npcm_i2c *bus,
2043 if (bus->state != I2C_IDLE) {
2044 bus->cmd_err = -EBUSY;
2047 bus->dest_addr = slave_addr << 1;
2048 bus->wr_buf = write_data;
2049 bus->wr_size = nwrite;
2050 bus->wr_ind = 0;
2051 bus->rd_buf = read_data;
2052 bus->rd_size = nread;
2053 bus->rd_ind = 0;
2054 bus->PEC_use = 0;
2058 bus->PEC_use = use_PEC;
2060 bus->read_block_use = use_read_block;
2062 bus->operation = I2C_READ_OPER;
2064 bus->operation = I2C_WRITE_OPER;
2065 if (bus->fifo_use) {
2068 npcm_i2c_select_bank(bus, I2C_BANK_1);
2070 i2cfif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS);
2073 iowrite8(i2cfif_cts, bus->reg + NPCM_I2CFIF_CTS);
2076 bus->state = I2C_IDLE;
2077 npcm_i2c_stall_after_start(bus, true);
2078 npcm_i2c_master_start(bus);
2085 struct npcm_i2c *bus = container_of(adap, struct npcm_i2c, adap);
2097 if (bus->state == I2C_DISABLE) {
2098 dev_err(bus->dev, "I2C%d module is disabled", bus->num);
2141 timeout_usec = (2 * 9 * USEC_PER_SEC / bus->bus_freq) * (2 + nread + nwrite);
2142 timeout = max_t(unsigned long, bus->adap.timeout, usecs_to_jiffies(timeout_usec));
2144 dev_err(bus->dev, "i2c%d buffer too big\n", bus->num);
2151 * we must clear slave address immediately when the bus is not
2155 spin_lock_irqsave(&bus->lock, flags);
2156 bus_busy = ioread8(bus->reg + NPCM_I2CCST) & NPCM_I2CCST_BB;
2158 if (!bus_busy && bus->slave)
2159 iowrite8((bus->slave->addr & 0x7F),
2160 bus->reg + NPCM_I2CADDR1);
2162 spin_unlock_irqrestore(&bus->lock, flags);
2167 iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST);
2168 npcm_i2c_reset(bus);
2173 npcm_i2c_init_params(bus);
2174 bus->dest_addr = slave_addr;
2175 bus->msgs = msgs;
2176 bus->msgs_num = num;
2177 bus->cmd_err = 0;
2178 bus->read_block_use = read_block;
2180 reinit_completion(&bus->cmd_complete);
2182 npcm_i2c_int_enable(bus, true);
2184 if (npcm_i2c_master_start_xmit(bus, slave_addr, nwrite, nread,
2187 time_left = wait_for_completion_timeout(&bus->cmd_complete,
2191 if (bus->timeout_cnt < ULLONG_MAX)
2192 bus->timeout_cnt++;
2193 if (bus->master_or_slave == I2C_MASTER) {
2195 bus->cmd_err = -EIO;
2196 bus->state = I2C_IDLE;
2201 /* if there was BER, check if need to recover the bus: */
2202 if (bus->cmd_err == -EAGAIN)
2203 bus->cmd_err = i2c_recover_bus(adap);
2210 else if (bus->cmd_err &&
2211 (bus->data->rxf_ctl_last_pec & ioread8(bus->reg + NPCM_I2CRXF_CTL)))
2212 npcm_i2c_reset(bus);
2215 npcm_i2c_stall_after_start(bus, false);
2216 npcm_i2c_eob_int(bus, false);
2220 if (bus->slave)
2221 iowrite8((bus->slave->addr & 0x7F) | NPCM_I2CADDR_SAEN,
2222 bus->reg + NPCM_I2CADDR1);
2224 npcm_i2c_int_enable(bus, false);
2226 return bus->cmd_err;
2257 struct npcm_i2c *bus)
2266 debugfs_create_u64("ber_cnt", 0444, d, &bus->ber_cnt);
2267 debugfs_create_u64("nack_cnt", 0444, d, &bus->nack_cnt);
2268 debugfs_create_u64("rec_succ_cnt", 0444, d, &bus->rec_succ_cnt);
2269 debugfs_create_u64("rec_fail_cnt", 0444, d, &bus->rec_fail_cnt);
2270 debugfs_create_u64("timeout_cnt", 0444, d, &bus->timeout_cnt);
2271 debugfs_create_u64("tx_complete_cnt", 0444, d, &bus->tx_complete_cnt);
2273 bus->debugfs = d;
2282 struct npcm_i2c *bus;
2287 bus = devm_kzalloc(&pdev->dev, sizeof(*bus), GFP_KERNEL);
2288 if (!bus)
2291 bus->dev = &pdev->dev;
2293 bus->data = of_device_get_match_data(dev);
2294 if (!bus->data) {
2299 bus->num = of_alias_get_id(pdev->dev.of_node, "i2c");
2304 bus->apb_clk = clk_get_rate(i2c_clk);
2312 regmap_write(gcr_regmap, NPCM_I2CSEGCTL, bus->data->segctl_init_val);
2314 bus->reg = devm_platform_ioremap_resource(pdev, 0);
2315 if (IS_ERR(bus->reg))
2316 return PTR_ERR(bus->reg);
2318 spin_lock_init(&bus->lock);
2319 init_completion(&bus->cmd_complete);
2321 adap = &bus->adap;
2327 adap->algo_data = bus;
2336 ret = devm_request_irq(bus->dev, irq, npcm_i2c_bus_irq, 0,
2337 dev_name(bus->dev), bus);
2341 ret = __npcm_i2c_init(bus, pdev);
2347 i2c_set_adapdata(adap, bus);
2349 snprintf(bus->adap.name, sizeof(bus->adap.name), "npcm_i2c_%d",
2350 bus->num);
2351 ret = i2c_add_numbered_adapter(&bus->adap);
2355 platform_set_drvdata(pdev, bus);
2356 npcm_i2c_init_debugfs(pdev, bus);
2363 struct npcm_i2c *bus = platform_get_drvdata(pdev);
2365 debugfs_remove_recursive(bus->debugfs);
2366 spin_lock_irqsave(&bus->lock, lock_flags);
2367 npcm_i2c_disable(bus);
2368 spin_unlock_irqrestore(&bus->lock, lock_flags);
2369 i2c_del_adapter(&bus->adap);