Lines Matching defs:drv_data
177 mv64xxx_i2c_prepare_for_io(struct mv64xxx_i2c_data *drv_data,
182 drv_data->cntl_bits = MV64XXX_I2C_REG_CONTROL_ACK |
185 if (!drv_data->atomic)
186 drv_data->cntl_bits |= MV64XXX_I2C_REG_CONTROL_INTEN;
192 drv_data->addr1 = 0xf0 | (((u32)msg->addr & 0x300) >> 7) | dir;
193 drv_data->addr2 = (u32)msg->addr & 0xff;
195 drv_data->addr1 = MV64XXX_I2C_ADDR_ADDR((u32)msg->addr) | dir;
196 drv_data->addr2 = 0;
210 mv64xxx_i2c_hw_init(struct mv64xxx_i2c_data *drv_data)
212 if (drv_data->offload_enabled) {
213 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
214 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_TIMING);
215 writel(0, drv_data->reg_base +
217 writel(0, drv_data->reg_base +
221 writel(0, drv_data->reg_base + drv_data->reg_offsets.soft_reset);
222 writel(MV64XXX_I2C_BAUD_DIV_M(drv_data->freq_m) | MV64XXX_I2C_BAUD_DIV_N(drv_data->freq_n),
223 drv_data->reg_base + drv_data->reg_offsets.clock);
224 writel(0, drv_data->reg_base + drv_data->reg_offsets.addr);
225 writel(0, drv_data->reg_base + drv_data->reg_offsets.ext_addr);
227 drv_data->reg_base + drv_data->reg_offsets.control);
229 if (drv_data->errata_delay)
232 drv_data->state = MV64XXX_I2C_STATE_IDLE;
236 mv64xxx_i2c_fsm(struct mv64xxx_i2c_data *drv_data, u32 status)
243 if (drv_data->state == MV64XXX_I2C_STATE_IDLE) {
244 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
253 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_1;
254 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK;
259 if (drv_data->msg->flags & I2C_M_TEN) {
260 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2;
261 drv_data->state =
268 if ((drv_data->bytes_left == 0)
269 || (drv_data->aborting
270 && (drv_data->byte_posn != 0))) {
271 if (drv_data->send_stop || drv_data->aborting) {
272 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
273 drv_data->state = MV64XXX_I2C_STATE_IDLE;
275 drv_data->action =
277 drv_data->state =
281 drv_data->action = MV64XXX_I2C_ACTION_SEND_DATA;
282 drv_data->state =
284 drv_data->bytes_left--;
290 if (drv_data->msg->flags & I2C_M_TEN) {
291 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2;
292 drv_data->state =
298 if (drv_data->bytes_left == 0) {
299 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
300 drv_data->state = MV64XXX_I2C_STATE_IDLE;
306 drv_data->action = MV64XXX_I2C_ACTION_CONTINUE;
308 drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA;
309 drv_data->bytes_left--;
311 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA;
313 if ((drv_data->bytes_left == 1) || drv_data->aborting)
314 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_ACK;
318 drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA_STOP;
319 drv_data->state = MV64XXX_I2C_STATE_IDLE;
326 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
327 drv_data->state = MV64XXX_I2C_STATE_IDLE;
328 drv_data->rc = -ENXIO;
332 dev_err(&drv_data->adapter.dev,
335 drv_data->state, status, drv_data->msg->addr,
336 drv_data->msg->flags);
337 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
338 mv64xxx_i2c_hw_init(drv_data);
339 i2c_recover_bus(&drv_data->adapter);
340 drv_data->rc = -EAGAIN;
344 static void mv64xxx_i2c_send_start(struct mv64xxx_i2c_data *drv_data)
346 drv_data->msg = drv_data->msgs;
347 drv_data->byte_posn = 0;
348 drv_data->bytes_left = drv_data->msg->len;
349 drv_data->aborting = 0;
350 drv_data->rc = 0;
352 mv64xxx_i2c_prepare_for_io(drv_data, drv_data->msgs);
353 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_START,
354 drv_data->reg_base + drv_data->reg_offsets.control);
358 mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data)
360 switch(drv_data->action) {
363 BUG_ON(drv_data->num_msgs == 0);
365 drv_data->msgs++;
366 drv_data->num_msgs--;
367 mv64xxx_i2c_send_start(drv_data);
369 if (drv_data->errata_delay)
377 drv_data->send_stop = drv_data->num_msgs == 1;
381 writel(drv_data->cntl_bits,
382 drv_data->reg_base + drv_data->reg_offsets.control);
386 writel(drv_data->addr1,
387 drv_data->reg_base + drv_data->reg_offsets.data);
388 writel(drv_data->cntl_bits,
389 drv_data->reg_base + drv_data->reg_offsets.control);
393 writel(drv_data->addr2,
394 drv_data->reg_base + drv_data->reg_offsets.data);
395 writel(drv_data->cntl_bits,
396 drv_data->reg_base + drv_data->reg_offsets.control);
400 writel(drv_data->msg->buf[drv_data->byte_posn++],
401 drv_data->reg_base + drv_data->reg_offsets.data);
402 writel(drv_data->cntl_bits,
403 drv_data->reg_base + drv_data->reg_offsets.control);
407 drv_data->msg->buf[drv_data->byte_posn++] =
408 readl(drv_data->reg_base + drv_data->reg_offsets.data);
409 writel(drv_data->cntl_bits,
410 drv_data->reg_base + drv_data->reg_offsets.control);
414 drv_data->msg->buf[drv_data->byte_posn++] =
415 readl(drv_data->reg_base + drv_data->reg_offsets.data);
416 if (!drv_data->atomic)
417 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
418 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
419 drv_data->reg_base + drv_data->reg_offsets.control);
420 drv_data->block = 0;
421 if (drv_data->errata_delay)
424 wake_up(&drv_data->waitq);
429 dev_err(&drv_data->adapter.dev,
431 drv_data->action);
432 drv_data->rc = -EIO;
435 if (!drv_data->atomic)
436 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
437 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
438 drv_data->reg_base + drv_data->reg_offsets.control);
439 drv_data->block = 0;
440 wake_up(&drv_data->waitq);
446 mv64xxx_i2c_read_offload_rx_data(struct mv64xxx_i2c_data *drv_data,
451 buf[0] = readl(drv_data->reg_base + MV64XXX_I2C_REG_RX_DATA_LO);
452 buf[1] = readl(drv_data->reg_base + MV64XXX_I2C_REG_RX_DATA_HI);
458 mv64xxx_i2c_intr_offload(struct mv64xxx_i2c_data *drv_data)
462 cause = readl(drv_data->reg_base +
467 status = readl(drv_data->reg_base +
471 drv_data->rc = -EIO;
475 drv_data->rc = 0;
481 if (drv_data->num_msgs == 1 && drv_data->msgs[0].flags & I2C_M_RD) {
482 mv64xxx_i2c_read_offload_rx_data(drv_data, drv_data->msgs);
483 drv_data->msgs++;
484 drv_data->num_msgs--;
490 else if (drv_data->num_msgs == 2 &&
491 !(drv_data->msgs[0].flags & I2C_M_RD) &&
492 drv_data->msgs[1].flags & I2C_M_RD) {
493 mv64xxx_i2c_read_offload_rx_data(drv_data, drv_data->msgs + 1);
494 drv_data->msgs += 2;
495 drv_data->num_msgs -= 2;
499 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
500 writel(0, drv_data->reg_base +
502 drv_data->block = 0;
504 wake_up(&drv_data->waitq);
512 struct mv64xxx_i2c_data *drv_data = dev_id;
516 spin_lock(&drv_data->lock);
518 if (drv_data->offload_enabled)
519 rc = mv64xxx_i2c_intr_offload(drv_data);
521 while (readl(drv_data->reg_base + drv_data->reg_offsets.control) &
531 if (drv_data->atomic)
534 status = readl(drv_data->reg_base + drv_data->reg_offsets.status);
535 mv64xxx_i2c_fsm(drv_data, status);
536 mv64xxx_i2c_do_action(drv_data);
538 if (drv_data->irq_clear_inverted)
539 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_IFLG,
540 drv_data->reg_base + drv_data->reg_offsets.control);
544 spin_unlock(&drv_data->lock);
557 mv64xxx_i2c_wait_for_completion(struct mv64xxx_i2c_data *drv_data)
563 time_left = wait_event_timeout(drv_data->waitq,
564 !drv_data->block, drv_data->adapter.timeout);
566 spin_lock_irqsave(&drv_data->lock, flags);
568 drv_data->rc = -ETIMEDOUT;
571 drv_data->rc = time_left; /* errno value */
575 if (abort && drv_data->block) {
576 drv_data->aborting = 1;
577 spin_unlock_irqrestore(&drv_data->lock, flags);
579 time_left = wait_event_timeout(drv_data->waitq,
580 !drv_data->block, drv_data->adapter.timeout);
582 if ((time_left <= 0) && drv_data->block) {
583 drv_data->state = MV64XXX_I2C_STATE_IDLE;
584 dev_err(&drv_data->adapter.dev,
586 "time_left: %d\n", drv_data->block,
588 mv64xxx_i2c_hw_init(drv_data);
589 i2c_recover_bus(&drv_data->adapter);
592 spin_unlock_irqrestore(&drv_data->lock, flags);
595 static void mv64xxx_i2c_wait_polling(struct mv64xxx_i2c_data *drv_data)
597 ktime_t timeout = ktime_add_ms(ktime_get(), drv_data->adapter.timeout);
599 while (READ_ONCE(drv_data->block) &&
602 mv64xxx_i2c_intr(0, drv_data);
607 mv64xxx_i2c_execute_msg(struct mv64xxx_i2c_data *drv_data, struct i2c_msg *msg,
612 spin_lock_irqsave(&drv_data->lock, flags);
614 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_START_COND;
616 drv_data->send_stop = is_last;
617 drv_data->block = 1;
618 mv64xxx_i2c_send_start(drv_data);
619 spin_unlock_irqrestore(&drv_data->lock, flags);
621 if (!drv_data->atomic)
622 mv64xxx_i2c_wait_for_completion(drv_data);
624 mv64xxx_i2c_wait_polling(drv_data);
626 return drv_data->rc;
630 mv64xxx_i2c_prepare_tx(struct mv64xxx_i2c_data *drv_data)
632 struct i2c_msg *msg = drv_data->msgs;
637 writel(buf[0], drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_LO);
638 writel(buf[1], drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_HI);
642 mv64xxx_i2c_offload_xfer(struct mv64xxx_i2c_data *drv_data)
644 struct i2c_msg *msgs = drv_data->msgs;
645 int num = drv_data->num_msgs;
649 spin_lock_irqsave(&drv_data->lock, flags);
664 mv64xxx_i2c_prepare_tx(drv_data);
687 mv64xxx_i2c_prepare_tx(drv_data);
691 drv_data->block = 1;
692 writel(ctrl_reg, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
693 spin_unlock_irqrestore(&drv_data->lock, flags);
695 mv64xxx_i2c_wait_for_completion(drv_data);
697 return drv_data->rc;
707 mv64xxx_i2c_can_offload(struct mv64xxx_i2c_data *drv_data)
709 struct i2c_msg *msgs = drv_data->msgs;
710 int num = drv_data->num_msgs;
712 if (!drv_data->offload_enabled)
754 struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap);
761 BUG_ON(drv_data->msgs != NULL);
762 drv_data->msgs = msgs;
763 drv_data->num_msgs = num;
765 if (mv64xxx_i2c_can_offload(drv_data) && !drv_data->atomic)
766 rc = mv64xxx_i2c_offload_xfer(drv_data);
768 rc = mv64xxx_i2c_execute_msg(drv_data, &msgs[0], num == 1);
773 drv_data->num_msgs = 0;
774 drv_data->msgs = NULL;
785 struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap);
787 drv_data->atomic = 0;
794 struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap);
796 drv_data->atomic = 1;
825 mv64xxx_calc_freq(struct mv64xxx_i2c_data *drv_data,
828 if (drv_data->clk_n_base_0)
835 mv64xxx_find_baud_factors(struct mv64xxx_i2c_data *drv_data,
843 freq = mv64xxx_calc_freq(drv_data, tclk, n, m);
846 drv_data->freq_m = m;
847 drv_data->freq_n = n;
859 mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data,
871 if (!drv_data->clk) {
875 tclk = clk_get_rate(drv_data->clk);
882 drv_data->clk_n_base_0 = true;
884 if (!mv64xxx_find_baud_factors(drv_data, bus_freq, tclk)) {
889 drv_data->rstc = devm_reset_control_get_optional_exclusive(dev, NULL);
890 if (IS_ERR(drv_data->rstc)) {
891 rc = PTR_ERR(drv_data->rstc);
898 drv_data->adapter.timeout = HZ;
904 memcpy(&drv_data->reg_offsets, device->data, sizeof(drv_data->reg_offsets));
911 drv_data->offload_enabled = true;
914 drv_data->errata_delay = true;
918 drv_data->offload_enabled = false;
921 drv_data->errata_delay = true;
925 drv_data->irq_clear_inverted = true;
932 mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data,
939 static int mv64xxx_i2c_init_recovery_info(struct mv64xxx_i2c_data *drv_data,
942 struct i2c_bus_recovery_info *rinfo = &drv_data->rinfo;
954 drv_data->adapter.bus_recovery_info = rinfo;
961 struct mv64xxx_i2c_data *drv_data = dev_get_drvdata(dev);
963 reset_control_assert(drv_data->rstc);
964 clk_disable_unprepare(drv_data->reg_clk);
965 clk_disable_unprepare(drv_data->clk);
973 struct mv64xxx_i2c_data *drv_data = dev_get_drvdata(dev);
975 clk_prepare_enable(drv_data->clk);
976 clk_prepare_enable(drv_data->reg_clk);
977 reset_control_reset(drv_data->rstc);
979 mv64xxx_i2c_hw_init(drv_data);
987 struct mv64xxx_i2c_data *drv_data;
994 drv_data = devm_kzalloc(&pd->dev, sizeof(struct mv64xxx_i2c_data),
996 if (!drv_data)
999 drv_data->reg_base = devm_platform_ioremap_resource(pd, 0);
1000 if (IS_ERR(drv_data->reg_base))
1001 return PTR_ERR(drv_data->reg_base);
1003 strscpy(drv_data->adapter.name, MV64XXX_I2C_CTLR_NAME " adapter",
1004 sizeof(drv_data->adapter.name));
1006 init_waitqueue_head(&drv_data->waitq);
1007 spin_lock_init(&drv_data->lock);
1010 drv_data->clk = devm_clk_get(&pd->dev, NULL);
1011 if (IS_ERR(drv_data->clk)) {
1012 if (PTR_ERR(drv_data->clk) == -EPROBE_DEFER)
1014 drv_data->clk = NULL;
1017 drv_data->reg_clk = devm_clk_get(&pd->dev, "reg");
1018 if (IS_ERR(drv_data->reg_clk)) {
1019 if (PTR_ERR(drv_data->reg_clk) == -EPROBE_DEFER)
1021 drv_data->reg_clk = NULL;
1024 drv_data->irq = platform_get_irq(pd, 0);
1025 if (drv_data->irq < 0)
1026 return drv_data->irq;
1029 drv_data->freq_m = pdata->freq_m;
1030 drv_data->freq_n = pdata->freq_n;
1031 drv_data->adapter.timeout = msecs_to_jiffies(pdata->timeout);
1032 drv_data->offload_enabled = false;
1033 memcpy(&drv_data->reg_offsets, &mv64xxx_i2c_regs_mv64xxx, sizeof(drv_data->reg_offsets));
1035 rc = mv64xxx_of_config(drv_data, &pd->dev);
1040 rc = mv64xxx_i2c_init_recovery_info(drv_data, &pd->dev);
1044 drv_data->adapter.dev.parent = &pd->dev;
1045 drv_data->adapter.algo = &mv64xxx_i2c_algo;
1046 drv_data->adapter.owner = THIS_MODULE;
1047 drv_data->adapter.class = I2C_CLASS_DEPRECATED;
1048 drv_data->adapter.nr = pd->id;
1049 drv_data->adapter.dev.of_node = pd->dev.of_node;
1050 platform_set_drvdata(pd, drv_data);
1051 i2c_set_adapdata(&drv_data->adapter, drv_data);
1062 rc = request_irq(drv_data->irq, mv64xxx_i2c_intr, 0,
1063 MV64XXX_I2C_CTLR_NAME, drv_data);
1065 dev_err(&drv_data->adapter.dev,
1067 drv_data->irq, rc);
1069 } else if ((rc = i2c_add_numbered_adapter(&drv_data->adapter)) != 0) {
1070 dev_err(&drv_data->adapter.dev,
1078 free_irq(drv_data->irq, drv_data);
1090 struct mv64xxx_i2c_data *drv_data = platform_get_drvdata(pd);
1092 i2c_del_adapter(&drv_data->adapter);
1093 free_irq(drv_data->irq, drv_data);