Lines Matching defs:dev
288 struct device *dev;
861 dev_dbg(i2c->dev, "Unsupported speed (%uhz)\n", target_speed);
948 dev_dbg(i2c->dev, "SLAVE_ADDR: 0x%x, INTR_MASK: 0x%x\n",
951 dev_dbg(i2c->dev, "INTR_STAT: 0x%x, CONTROL: 0x%x\n",
954 dev_dbg(i2c->dev, "TRANSFER_LEN: 0x%x, TRANSAC_LEN: 0x%x\n",
957 dev_dbg(i2c->dev, "DELAY_LEN: 0x%x, HTIMING: 0x%x\n",
960 dev_dbg(i2c->dev, "START: 0x%x, EXT_CONF: 0x%x\n",
963 dev_dbg(i2c->dev, "HS: 0x%x, IO_CONFIG: 0x%x\n",
966 dev_dbg(i2c->dev, "DCM_EN: 0x%x, TRANSFER_LEN_AUX: 0x%x\n",
969 dev_dbg(i2c->dev, "CLOCK_DIV: 0x%x, FIFO_STAT: 0x%x\n",
972 dev_dbg(i2c->dev, "DEBUGCTRL : 0x%x, DEBUGSTAT: 0x%x\n",
976 dev_dbg(i2c->dev, "LTIMING: 0x%x, MULTI_DMA: 0x%x\n",
980 dev_dbg(i2c->dev, "\nDMA_INT_FLAG: 0x%x, DMA_INT_EN: 0x%x\n",
983 dev_dbg(i2c->dev, "DMA_EN: 0x%x, DMA_CON: 0x%x\n",
986 dev_dbg(i2c->dev, "DMA_TX_MEM_ADDR: 0x%x, DMA_RX_MEM_ADDR: 0x%x\n",
989 dev_dbg(i2c->dev, "DMA_TX_LEN: 0x%x, DMA_RX_LEN: 0x%x\n",
992 dev_dbg(i2c->dev, "DMA_TX_4G_MODE: 0x%x, DMA_RX_4G_MODE: 0x%x",
1031 dev_err(i2c->dev, "DMA warm reset timeout\n");
1096 rpaddr = dma_map_single(i2c->dev, dma_rd_buf,
1098 if (dma_mapping_error(i2c->dev, rpaddr)) {
1119 wpaddr = dma_map_single(i2c->dev, dma_wr_buf,
1121 if (dma_mapping_error(i2c->dev, wpaddr)) {
1142 wpaddr = dma_map_single(i2c->dev, dma_wr_buf,
1144 if (dma_mapping_error(i2c->dev, wpaddr)) {
1152 dma_unmap_single(i2c->dev, wpaddr,
1160 rpaddr = dma_map_single(i2c->dev, dma_rd_buf,
1163 if (dma_mapping_error(i2c->dev, rpaddr)) {
1164 dma_unmap_single(i2c->dev, wpaddr,
1206 dma_unmap_single(i2c->dev, wpaddr,
1211 dma_unmap_single(i2c->dev, rpaddr,
1216 dma_unmap_single(i2c->dev, wpaddr, msgs->len,
1218 dma_unmap_single(i2c->dev, rpaddr, (msgs + 1)->len,
1226 dev_dbg(i2c->dev, "addr: %x, transfer timeout\n", msgs->addr);
1233 dev_dbg(i2c->dev, "addr: %x, transfer ACK error\n", msgs->addr);
1273 dev_dbg(i2c->dev, "data buffer is NULL.\n");
1371 i2c_parse_fw_timings(i2c->dev, &i2c->timing_info, true);
1382 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
1400 i2c->dev_comp = of_device_get_match_data(&pdev->dev);
1401 i2c->adap.dev.of_node = pdev->dev.of_node;
1402 i2c->dev = &pdev->dev;
1403 i2c->adap.dev.parent = &pdev->dev;
1409 i2c->adap.bus_regulator = devm_regulator_get_optional(&pdev->dev, "vbus");
1417 ret = mtk_i2c_parse_dt(pdev->dev.of_node, i2c);
1429 i2c->clocks[I2C_MT65XX_CLK_MAIN].clk = devm_clk_get(&pdev->dev, "main");
1431 dev_err(&pdev->dev, "cannot get main clock\n");
1435 i2c->clocks[I2C_MT65XX_CLK_DMA].clk = devm_clk_get(&pdev->dev, "dma");
1437 dev_err(&pdev->dev, "cannot get dma clock\n");
1441 i2c->clocks[I2C_MT65XX_CLK_ARB].clk = devm_clk_get_optional(&pdev->dev, "arb");
1446 i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = devm_clk_get(&pdev->dev, "pmic");
1448 dev_err(&pdev->dev, "cannot get pmic clock\n");
1461 dev_err(&pdev->dev, "Failed to set the speed.\n");
1466 ret = dma_set_mask(&pdev->dev,
1469 dev_err(&pdev->dev, "dma_set_mask return error.\n");
1476 dev_err(&pdev->dev, "clock enable failed!\n");
1482 ret = devm_request_irq(&pdev->dev, irq, mtk_i2c_irq,
1484 dev_name(&pdev->dev), i2c);
1486 dev_err(&pdev->dev,
1515 static int mtk_i2c_suspend_noirq(struct device *dev)
1517 struct mtk_i2c *i2c = dev_get_drvdata(dev);
1525 static int mtk_i2c_resume_noirq(struct device *dev)
1528 struct mtk_i2c *i2c = dev_get_drvdata(dev);
1532 dev_err(dev, "clock enable failed!\n");