Lines Matching defs:slave
268 /* SMBus slave GW. */
274 /* SMBus slave Finite State Machine (FSM). */
282 /* SMBus slave GW control bits offset in MLXBF_I2C_SMBUS_SLAVE_GW[31:19]. */
292 /* SMBus slave GW Data descriptor. */
296 /* SMbus slave configuration registers. */
388 u8 slave;
426 struct i2c_client *slave[MLXBF_I2C_SMBUS_SLAVE_ADDR_CNT];
696 static int mlxbf_i2c_smbus_enable(struct mlxbf_i2c_priv *priv, u8 slave,
709 command |= rol32(slave, MLXBF_I2C_MASTER_SLV_ADDR_SHIFT);
741 u8 slave, flags, addr;
756 slave = request->slave & GENMASK(6, 0);
757 addr = slave << 1;
818 data_len = write_len + 1; /* Add one byte of the slave address. */
820 * Note that data_len cannot be 0. Indeed, the slave address byte
827 ret = mlxbf_i2c_smbus_enable(priv, slave, write_len, block_en,
834 /* Write slave address to Master GW data descriptor. */
837 ret = mlxbf_i2c_smbus_enable(priv, slave, read_len, block_en,
1572 struct i2c_client *slave)
1583 * Read the slave registers. There are 4 * 32-bit slave registers.
1584 * Each slave register can hold up to 4 * 8-bit slave configuration:
1587 * Look for the next available slave register slot.
1593 * Each register holds 4 slave addresses. So, we have to keep
1604 * slave address slot associated with that bit is
1606 * slave address bits.
1610 slave_reg |= (slave->addr << (byte * 8));
1617 * Set the slave at the corresponding index.
1619 priv->slave[(reg * 4) + byte] = slave;
1640 * Read the slave registers. There are 4 * 32-bit slave registers.
1641 * Each slave register can hold up to 4 * 8-bit slave configuration:
1655 * Check if addr matches any of the 4 slave addresses
1662 * Parse slave address bytes and check whether the
1663 * slave address already exists.
1666 /* Clear the slave address slot. */
1671 /* Free slave at the corresponding index */
1672 priv->slave[(reg * 4) + byte] = NULL;
1775 * Enable slave cause interrupt bits. Drive
1850 if (!priv->slave[i])
1853 if (priv->slave[i]->addr == addr)
1854 return priv->slave[i];
1868 struct i2c_client *slave;
1874 * determine the slave address. This byte is located in the
1875 * first data descriptor register of the slave GW.
1882 * Check if the slave address received in the data descriptor register
1883 * matches any of the slave addresses registered. If there is a match,
1884 * set the slave.
1886 slave = mlxbf_i2c_get_slave_from_addr(priv, addr);
1887 if (!slave) {
1894 * a READ bit transaction. Indeed, slave devices often expect
1895 * the slave address to be followed by the internal address.
1900 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value);
1902 ret = i2c_slave_event(slave, I2C_SLAVE_WRITE_RECEIVED,
1904 i2c_slave_event(slave, I2C_SLAVE_STOP, &value);
1916 i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value);
1920 i2c_slave_event(slave, I2C_SLAVE_READ_PROCESSED, &value);
1924 i2c_slave_event(slave, I2C_SLAVE_STOP, &value);
1964 struct i2c_client *slave;
1974 * Check if the slave address received in the data descriptor register
1975 * matches any of the slave addresses registered.
1977 slave = mlxbf_i2c_get_slave_from_addr(priv, addr);
1978 if (!slave) {
1984 * Notify the slave backend that an smbus master wants to write data
1987 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value);
1989 /* Send the received data to the slave backend. */
1992 ret = i2c_slave_event(slave, I2C_SLAVE_WRITE_RECEIVED,
1999 * Send a stop event to the slave backend, to signal
2002 i2c_slave_event(slave, I2C_SLAVE_STOP, &value);
2025 * - Send data and release slave GW.
2040 * slave, if the higher 8 bits are sent then the slave expect N bytes
2048 * For now, the slave supports 128 bytes transfer. Discard remaining
2050 * MLXBF_I2C_SLAVE_DATA_DESC_SIZE, i.e, the actual size of the slave
2079 request.slave = addr;
2087 dev_dbg(&adap->dev, "smbus quick, slave 0x%02x\n", addr);
2094 dev_dbg(&adap->dev, "smbus %s byte, slave 0x%02x.\n",
2101 dev_dbg(&adap->dev, "smbus %s byte data at 0x%02x, slave 0x%02x.\n",
2108 dev_dbg(&adap->dev, "smbus %s word data at 0x%02x, slave 0x%02x.\n",
2116 dev_dbg(&adap->dev, "i2c %s block data, %d bytes at 0x%02x, slave 0x%02x.\n",
2124 dev_dbg(&adap->dev, "smbus %s block data, %d bytes at 0x%02x, slave 0x%02x.\n",
2131 dev_dbg(&adap->dev, "process call, wr/rd at 0x%02x, slave 0x%02x.\n",
2140 dev_dbg(&adap->dev, "block process call, wr/rd %d bytes, slave 0x%02x.\n",
2155 static int mlxbf_i2c_reg_slave(struct i2c_client *slave)
2157 struct mlxbf_i2c_priv *priv = i2c_get_adapdata(slave->adapter);
2158 struct device *dev = &slave->dev;
2165 if (slave->flags & (I2C_CLIENT_TEN | I2C_CLIENT_PEC)) {
2170 ret = mlxbf_i2c_slave_enable(priv, slave);
2177 static int mlxbf_i2c_unreg_slave(struct i2c_client *slave)
2179 struct mlxbf_i2c_priv *priv = i2c_get_adapdata(slave->adapter);
2180 struct device *dev = &slave->dev;
2184 * Unregister slave by:
2185 * 1) Disabling the slave address in hardware
2186 * 2) Freeing priv->slave at the corresponding index
2188 ret = mlxbf_i2c_slave_disable(priv, slave->addr);
2190 dev_err(dev, "Unable to find slave 0x%x\n", slave->addr);
2298 * separate resources "timer", "master" and "slave".
2340 return dev_err_probe(dev, ret, "Cannot fetch slave resource info");
2351 return dev_err_probe(dev, ret, "Cannot fetch cause slave resource info");