Lines Matching defs:frequency
62 * SMBus Master core clock frequency. Timing configurations are
63 * strongly dependent on the core clock frequency of the SMBus
70 /* Constant used to determine the PLL frequency. */
166 * Defines SMBus operating frequency and core clock frequency.
169 * frequency based on PLL parameters.
309 /* Polling frequency in microseconds. */
405 /* Callback to calculate the core PLL frequency. */
423 u64 frequency; /* Core frequency in Hz. */
430 /* Core PLL frequency. */
1099 u64 frequency;
1109 frequency = priv->frequency;
1110 ticks = (nanoseconds * frequency) / MLXBF_I2C_FREQUENCY_1GHZ;
1189 * bus frequency, it is impacted by the time it takes the driver to
1252 ret = device_property_read_u32(dev, "clock-frequency", &config_khz);
1480 * Compute PLL output frequency as follow:
1511 * Compute PLL output frequency as follow:
1532 u64 *freq = &priv->frequency;
1541 * First, check whether the TYU core Clock frequency is set.
1542 * The TYU core frequency is the same for all I2C busses; when
1543 * the first device gets probed the frequency is determined and
1545 * check whether the frequency is already set. Here, we assume
1546 * that the frequency is expected to be greater than 0.
2365 /* Read Core PLL frequency. */
2368 dev_err(dev, "cannot get core clock frequency\n");
2370 priv->frequency = MLXBF_I2C_COREPLL_FREQ;