Lines Matching defs:bits
87 * Cause Status flags. Note that those bits might be considered
88 * as interrupt enabled bits.
124 * Slave cause status flags. Note that those bits might be considered
125 * as interrupt enabled bits.
149 * SMBUS GW0 -> bits[26:25]
150 * SMBUS GW1 -> bits[28:27]
151 * SMBUS GW2 -> bits[30:29]
209 /* Status bits (ACK/NACK/FW Timeout). */
215 /* SMBus master GW control bits offset in MLXBF_I2C_SMBUS_MASTER_GW[31:3]. */
282 /* SMBus slave GW control bits offset in MLXBF_I2C_SMBUS_SLAVE_GW[31:19]. */
499 * Function to poll a set of bits at a specific address; it checks whether
500 * the bits are equal to zero when eq_zero is set to 'true', and not equal
507 u32 bits;
512 bits = readl(io + addr) & mask;
513 if (eq_zero ? bits == 0 : bits != 0)
514 return eq_zero ? 1 : bits;
591 * then read the cause and master status bits to determine if
598 /* Read cause status bits. */
604 * Parse both Cause and Master GW bits, then return transaction status.
617 * transaction ended bits cause will not be set so the transaction
618 * fails. Then, we must check Master GW status bits.
713 /* Clear status bits. */
726 * Poll master status and check status bits. An ACK is sent when
783 * bits such as block_en and pec_en. These bits MUST be
1474 /* Get Core PLL configuration bits. */
1505 /* Get Core PLL configuration bits */
1606 * slave address bits.
1775 * Enable slave cause interrupt bits. Drive
1826 /* Clear cause bits. */
2038 * bytes from/to master. These are defined by 8-bits each. If the lower
2039 * 8 bits are set, then the master expect to read N bytes from the
2040 * slave, if the higher 8 bits are sent then the slave expect N bytes