Lines Matching defs:i2c
14 #include <linux/i2c.h>
15 #include <linux/i2c-smbus.h>
334 static int set_sys_lock(struct pci1xxxx_i2c *i2c)
336 void __iomem *p = i2c->i2c_base + SMB_GPR_LOCK_REG;
347 static int release_sys_lock(struct pci1xxxx_i2c *i2c)
349 void __iomem *p = i2c->i2c_base + SMB_GPR_LOCK_REG;
364 static void pci1xxxx_ack_high_level_intr(struct pci1xxxx_i2c *i2c, u16 intr_msk)
366 writew(intr_msk, i2c->i2c_base + SMBUS_GEN_INT_STAT_REG_OFF);
369 static void pci1xxxx_i2c_configure_smbalert_pin(struct pci1xxxx_i2c *i2c,
372 void __iomem *p = i2c->i2c_base + SMBALERT_MST_PAD_CTRL_REG_OFF;
385 static void pci1xxxx_i2c_send_start_stop(struct pci1xxxx_i2c *i2c, bool start)
387 void __iomem *p = i2c->i2c_base + SMB_CORE_CMD_REG_OFF1;
405 static void pci1xxxx_i2c_set_clear_FW_ACK(struct pci1xxxx_i2c *i2c, bool set)
414 writeb(regval, i2c->i2c_base + SMB_CORE_CTRL_REG_OFF);
417 static void pci1xxxx_i2c_buffer_write(struct pci1xxxx_i2c *i2c, u8 slaveaddr,
420 void __iomem *p = i2c->i2c_base + SMBUS_MST_BUF;
434 static void pci1xxxx_i2c_enable_ESO(struct pci1xxxx_i2c *i2c)
436 writeb(SMB_CORE_CTRL_ESO, i2c->i2c_base + SMB_CORE_CTRL_REG_OFF);
439 static void pci1xxxx_i2c_reset_counters(struct pci1xxxx_i2c *i2c)
441 void __iomem *p = i2c->i2c_base + SMBUS_CONTROL_REG_OFF;
449 static void pci1xxxx_i2c_set_transfer_dir(struct pci1xxxx_i2c *i2c, u8 direction)
451 void __iomem *p = i2c->i2c_base + SMBUS_CONTROL_REG_OFF;
463 static void pci1xxxx_i2c_set_mcu_count(struct pci1xxxx_i2c *i2c, u8 count)
465 writeb(count, i2c->i2c_base + SMBUS_MCU_COUNTER_REG_OFF);
468 static void pci1xxxx_i2c_set_read_count(struct pci1xxxx_i2c *i2c, u8 readcount)
470 writeb(readcount, i2c->i2c_base + SMB_CORE_CMD_REG_OFF3);
473 static void pci1xxxx_i2c_set_write_count(struct pci1xxxx_i2c *i2c, u8 writecount)
475 writeb(writecount, i2c->i2c_base + SMB_CORE_CMD_REG_OFF2);
478 static void pci1xxxx_i2c_set_DMA_run(struct pci1xxxx_i2c *i2c)
480 void __iomem *p = i2c->i2c_base + SMBUS_CONTROL_REG_OFF;
488 static void pci1xxxx_i2c_set_mrun_proceed(struct pci1xxxx_i2c *i2c)
490 void __iomem *p = i2c->i2c_base + SMB_CORE_CMD_REG_OFF0;
499 static void pci1xxxx_i2c_start_DMA(struct pci1xxxx_i2c *i2c)
501 pci1xxxx_i2c_set_DMA_run(i2c);
502 pci1xxxx_i2c_set_mrun_proceed(i2c);
505 static void pci1xxxx_i2c_config_asr(struct pci1xxxx_i2c *i2c, bool enable)
507 void __iomem *p = i2c->i2c_base + SMB_CORE_CONFIG_REG1;
520 struct pci1xxxx_i2c *i2c = dev;
521 void __iomem *p1 = i2c->i2c_base + SMBUS_GEN_INT_STAT_REG_OFF;
522 void __iomem *p2 = i2c->i2c_base + SMBUS_INTR_STAT_REG_OFF;
536 complete(&i2c->i2c_xfer_done);
540 pci1xxxx_ack_high_level_intr(i2c, I2C_BUF_MSTR_INTR_MASK);
545 pci1xxxx_ack_high_level_intr(i2c, SMBALERT_INTR_MASK);
551 static void pci1xxxx_i2c_set_count(struct pci1xxxx_i2c *i2c, u8 mcucount,
554 pci1xxxx_i2c_set_mcu_count(i2c, mcucount);
555 pci1xxxx_i2c_set_write_count(i2c, writecount);
556 pci1xxxx_i2c_set_read_count(i2c, readcount);
559 static void pci1xxxx_i2c_set_readm(struct pci1xxxx_i2c *i2c, bool enable)
561 void __iomem *p = i2c->i2c_base + SMB_CORE_CMD_REG_OFF1;
573 static void pci1xxxx_ack_nw_layer_intr(struct pci1xxxx_i2c *i2c, u8 ack_intr_msk)
575 writeb(ack_intr_msk, i2c->i2c_base + SMBUS_INTR_STAT_REG_OFF);
578 static void pci1xxxx_config_nw_layer_intr(struct pci1xxxx_i2c *i2c,
581 void __iomem *p = i2c->i2c_base + SMBUS_INTR_MSK_REG_OFF;
593 static void pci1xxxx_i2c_config_padctrl(struct pci1xxxx_i2c *i2c, bool enable)
595 void __iomem *p1 = i2c->i2c_base + I2C_SCL_PAD_CTRL_REG_OFF;
596 void __iomem *p2 = i2c->i2c_base + I2C_SDA_PAD_CTRL_REG_OFF;
616 static void pci1xxxx_i2c_set_mode(struct pci1xxxx_i2c *i2c)
618 void __iomem *p = i2c->i2c_base + SMBUS_CONTROL_REG_OFF;
622 if (i2c->flags & I2C_FLAGS_DIRECT_MODE)
630 static void pci1xxxx_i2c_config_high_level_intr(struct pci1xxxx_i2c *i2c,
633 void __iomem *p = i2c->i2c_base + SMBUS_GEN_INT_MASK_REG_OFF;
644 static void pci1xxxx_i2c_configure_core_reg(struct pci1xxxx_i2c *i2c, bool enable)
646 void __iomem *p1 = i2c->i2c_base + SMB_CORE_CONFIG_REG1;
647 void __iomem *p3 = i2c->i2c_base + SMB_CORE_CONFIG_REG3;
665 static void pci1xxxx_i2c_set_freq(struct pci1xxxx_i2c *i2c)
667 void __iomem *bp = i2c->i2c_base;
675 switch (i2c->freq) {
706 static void pci1xxxx_i2c_init(struct pci1xxxx_i2c *i2c)
708 void __iomem *p2 = i2c->i2c_base + SMBUS_STATUS_REG_OFF;
709 void __iomem *p1 = i2c->i2c_base + SMB_GPR_REG;
713 ret = set_sys_lock(i2c);
722 release_sys_lock(i2c);
727 i2c->freq = I2C_MAX_FAST_MODE_FREQ;
728 pci1xxxx_i2c_set_freq(i2c);
731 i2c->freq = I2C_MAX_STANDARD_MODE_FREQ;
732 pci1xxxx_i2c_set_freq(i2c);
735 i2c->freq = I2C_MAX_FAST_MODE_PLUS_FREQ;
736 pci1xxxx_i2c_set_freq(i2c);
743 pci1xxxx_i2c_config_padctrl(i2c, true);
744 i2c->flags |= I2C_FLAGS_DIRECT_MODE;
745 pci1xxxx_i2c_set_mode(i2c);
754 pci1xxxx_i2c_configure_core_reg(i2c, true);
760 pci1xxxx_i2c_configure_smbalert_pin(i2c, true);
763 static void pci1xxxx_i2c_clear_flags(struct pci1xxxx_i2c *i2c)
768 pci1xxxx_i2c_reset_counters(i2c);
772 writeb(regval, i2c->i2c_base + SMB_CORE_COMPLETION_REG_OFF3);
773 reinit_completion(&i2c->i2c_xfer_done);
774 pci1xxxx_ack_nw_layer_intr(i2c, ALL_NW_LAYER_INTERRUPTS);
775 pci1xxxx_ack_high_level_intr(i2c, ALL_HIGH_LAYER_INTR);
778 static int pci1xxxx_i2c_read(struct pci1xxxx_i2c *i2c, u8 slaveaddr,
781 void __iomem *p2 = i2c->i2c_base + SMB_CORE_COMPLETION_REG_OFF3;
782 void __iomem *p1 = i2c->i2c_base + SMB_CORE_CMD_REG_OFF1;
783 void __iomem *p3 = i2c->i2c_base + SMBUS_MST_BUF;
793 pci1xxxx_i2c_enable_ESO(i2c);
794 pci1xxxx_i2c_clear_flags(i2c);
795 pci1xxxx_config_nw_layer_intr(i2c, INTR_MSK_DMA_TERM, true);
796 pci1xxxx_i2c_config_high_level_intr(i2c, I2C_BUF_MSTR_INTR_MASK, true);
827 (i2c->flags & I2C_FLAGS_STOP)) {
828 pci1xxxx_i2c_set_clear_FW_ACK(i2c, false);
829 pci1xxxx_i2c_send_start_stop(i2c, 0);
831 pci1xxxx_i2c_set_clear_FW_ACK(i2c, true);
836 pci1xxxx_i2c_set_transfer_dir(i2c, I2C_DIRN_WRITE);
837 pci1xxxx_i2c_send_start_stop(i2c, 1);
840 pci1xxxx_i2c_buffer_write(i2c, slaveaddr, 0, NULL);
843 pci1xxxx_i2c_set_count(i2c, 1, 1, transferlen);
849 pci1xxxx_i2c_config_asr(i2c, true);
850 if (i2c->flags & I2C_FLAGS_SMB_BLK_READ)
851 pci1xxxx_i2c_set_readm(i2c, true);
853 pci1xxxx_i2c_set_count(i2c, 0, 0, transferlen);
854 pci1xxxx_i2c_config_asr(i2c, false);
855 pci1xxxx_i2c_clear_flags(i2c);
856 pci1xxxx_i2c_set_transfer_dir(i2c, I2C_DIRN_READ);
860 pci1xxxx_i2c_start_DMA(i2c);
863 time_left = wait_for_completion_timeout(&i2c->i2c_xfer_done,
867 pci1xxxx_i2c_init(i2c);
882 if (i2c->flags & I2C_FLAGS_SMB_BLK_READ) {
893 pci1xxxx_config_nw_layer_intr(i2c, INTR_MSK_DMA_TERM, false);
894 pci1xxxx_i2c_config_high_level_intr(i2c, I2C_BUF_MSTR_INTR_MASK, false);
895 pci1xxxx_i2c_config_asr(i2c, false);
899 static int pci1xxxx_i2c_write(struct pci1xxxx_i2c *i2c, u8 slaveaddr,
902 void __iomem *p2 = i2c->i2c_base + SMB_CORE_COMPLETION_REG_OFF3;
903 void __iomem *p1 = i2c->i2c_base + SMB_CORE_CMD_REG_OFF1;
913 pci1xxxx_i2c_enable_ESO(i2c);
916 pci1xxxx_i2c_set_transfer_dir(i2c, I2C_DIRN_WRITE);
917 pci1xxxx_config_nw_layer_intr(i2c, INTR_MSK_DMA_TERM, true);
918 pci1xxxx_i2c_config_high_level_intr(i2c, I2C_BUF_MSTR_INTR_MASK, true);
921 * The i2c transfer could be more than 128 bytes. Our Core is
930 pci1xxxx_i2c_clear_flags(i2c);
935 pci1xxxx_i2c_send_start_stop(i2c, 1);
940 pci1xxxx_i2c_buffer_write(i2c, slaveaddr,
949 pci1xxxx_i2c_buffer_write(i2c, 0, transferlen, &buf[count]);
953 pci1xxxx_i2c_set_count(i2c, actualwritelen, actualwritelen, 0);
960 (i2c->flags & I2C_FLAGS_STOP))
961 pci1xxxx_i2c_send_start_stop(i2c, 0);
963 pci1xxxx_i2c_start_DMA(i2c);
968 time_left = wait_for_completion_timeout(&i2c->i2c_xfer_done,
972 pci1xxxx_i2c_init(i2c);
986 pci1xxxx_config_nw_layer_intr(i2c, INTR_MSK_DMA_TERM, false);
987 pci1xxxx_i2c_config_high_level_intr(i2c, I2C_BUF_MSTR_INTR_MASK, false);
995 struct pci1xxxx_i2c *i2c = i2c_get_adapdata(adap);
1000 i2c->i2c_xfer_in_progress = true;
1009 i2c->flags |= I2C_FLAGS_STOP;
1011 i2c->flags &= ~I2C_FLAGS_STOP;
1014 i2c->flags |= I2C_FLAGS_SMB_BLK_READ;
1016 i2c->flags &= ~I2C_FLAGS_SMB_BLK_READ;
1019 retval = pci1xxxx_i2c_read(i2c, slaveaddr,
1022 retval = pci1xxxx_i2c_write(i2c, slaveaddr,
1028 i2c->i2c_xfer_in_progress = false;
1068 struct pci1xxxx_i2c *i2c = dev_get_drvdata(dev);
1069 void __iomem *p = i2c->i2c_base + SMBUS_RESET_REG;
1073 i2c_mark_adapter_suspended(&i2c->adap);
1079 while (i2c->i2c_xfer_in_progress)
1082 pci1xxxx_i2c_config_high_level_intr(i2c, SMBALERT_WAKE_INTR_MASK, true);
1101 struct pci1xxxx_i2c *i2c = dev_get_drvdata(dev);
1102 void __iomem *p1 = i2c->i2c_base + SMBUS_GEN_INT_STAT_REG_OFF;
1103 void __iomem *p2 = i2c->i2c_base + SMBUS_RESET_REG;
1109 pci1xxxx_i2c_config_high_level_intr(i2c, SMBALERT_WAKE_INTR_MASK, false);
1113 i2c_mark_adapter_resumed(&i2c->adap);
1123 struct pci1xxxx_i2c *i2c = data;
1125 pci1xxxx_i2c_config_padctrl(i2c, false);
1126 pci1xxxx_i2c_configure_core_reg(i2c, false);
1133 struct pci1xxxx_i2c *i2c;
1136 i2c = devm_kzalloc(dev, sizeof(*i2c), GFP_KERNEL);
1137 if (!i2c)
1140 pci_set_drvdata(pdev, i2c);
1141 i2c->i2c_xfer_in_progress = false;
1157 i2c->i2c_base = pcim_iomap_table(pdev)[0];
1158 init_completion(&i2c->i2c_xfer_done);
1159 pci1xxxx_i2c_init(i2c);
1161 ret = devm_add_action(dev, pci1xxxx_i2c_shutdown, i2c);
1170 0, pci_name(pdev), i2c);
1174 i2c->adap = pci1xxxx_i2c_ops;
1175 i2c->adap.dev.parent = dev;
1177 snprintf(i2c->adap.name, sizeof(i2c->adap.name),
1178 "MCHP PCI1xxxx i2c adapter at %s", pci_name(pdev));
1180 i2c_set_adapdata(&i2c->adap, i2c);
1182 ret = devm_i2c_add_adapter(dev, &i2c->adap);
1184 return dev_err_probe(dev, ret, "i2c add adapter failed\n");
1200 .name = "i2c-mchp-pci1xxxx",