Lines Matching refs:ctlr
112 static void hisi_i2c_enable_int(struct hisi_i2c_controller *ctlr, u32 mask)
114 writel_relaxed(mask, ctlr->iobase + HISI_I2C_INT_MASK);
117 static void hisi_i2c_disable_int(struct hisi_i2c_controller *ctlr, u32 mask)
119 writel_relaxed((~mask) & HISI_I2C_INT_ALL, ctlr->iobase + HISI_I2C_INT_MASK);
122 static void hisi_i2c_clear_int(struct hisi_i2c_controller *ctlr, u32 mask)
124 writel_relaxed(mask, ctlr->iobase + HISI_I2C_INT_CLR);
127 static void hisi_i2c_handle_errors(struct hisi_i2c_controller *ctlr)
129 u32 int_err = ctlr->xfer_err, reg;
132 reg = readl(ctlr->iobase + HISI_I2C_FIFO_STATE);
135 dev_err(ctlr->dev, "rx fifo error read\n");
138 dev_err(ctlr->dev, "rx fifo error write\n");
141 dev_err(ctlr->dev, "tx fifo error read\n");
144 dev_err(ctlr->dev, "tx fifo error write\n");
148 static int hisi_i2c_start_xfer(struct hisi_i2c_controller *ctlr)
150 struct i2c_msg *msg = ctlr->msgs;
153 reg = readl(ctlr->iobase + HISI_I2C_FRAME_CTRL);
157 writel(reg, ctlr->iobase + HISI_I2C_FRAME_CTRL);
159 reg = readl(ctlr->iobase + HISI_I2C_SLV_ADDR);
162 writel(reg, ctlr->iobase + HISI_I2C_SLV_ADDR);
164 reg = readl(ctlr->iobase + HISI_I2C_FIFO_CTRL);
166 writel(reg, ctlr->iobase + HISI_I2C_FIFO_CTRL);
168 writel(reg, ctlr->iobase + HISI_I2C_FIFO_CTRL);
170 hisi_i2c_clear_int(ctlr, HISI_I2C_INT_ALL);
171 hisi_i2c_enable_int(ctlr, HISI_I2C_INT_ALL);
176 static void hisi_i2c_reset_xfer(struct hisi_i2c_controller *ctlr)
178 ctlr->msg_num = 0;
179 ctlr->xfer_err = 0;
180 ctlr->msg_tx_idx = 0;
181 ctlr->msg_rx_idx = 0;
182 ctlr->buf_tx_idx = 0;
183 ctlr->buf_rx_idx = 0;
195 struct hisi_i2c_controller *ctlr = i2c_get_adapdata(adap);
199 hisi_i2c_reset_xfer(ctlr);
200 ctlr->completion = &done;
201 ctlr->msg_num = num;
202 ctlr->msgs = msgs;
204 hisi_i2c_start_xfer(ctlr);
206 if (!wait_for_completion_timeout(ctlr->completion, adap->timeout)) {
207 hisi_i2c_disable_int(ctlr, HISI_I2C_INT_ALL);
208 synchronize_irq(ctlr->irq);
209 i2c_recover_bus(&ctlr->adapter);
210 dev_err(ctlr->dev, "bus transfer timeout\n");
214 if (ctlr->xfer_err) {
215 hisi_i2c_handle_errors(ctlr);
219 hisi_i2c_reset_xfer(ctlr);
220 ctlr->completion = NULL;
235 static int hisi_i2c_read_rx_fifo(struct hisi_i2c_controller *ctlr)
240 while (ctlr->msg_rx_idx < ctlr->msg_num) {
241 cur_msg = ctlr->msgs + ctlr->msg_rx_idx;
244 ctlr->msg_rx_idx++;
248 fifo_state = readl(ctlr->iobase + HISI_I2C_FIFO_STATE);
250 ctlr->buf_rx_idx < cur_msg->len) {
251 cur_msg->buf[ctlr->buf_rx_idx++] = readl(ctlr->iobase + HISI_I2C_RXDATA);
252 fifo_state = readl(ctlr->iobase + HISI_I2C_FIFO_STATE);
255 if (ctlr->buf_rx_idx == cur_msg->len) {
256 ctlr->buf_rx_idx = 0;
257 ctlr->msg_rx_idx++;
267 static void hisi_i2c_xfer_msg(struct hisi_i2c_controller *ctlr)
274 while (ctlr->msg_tx_idx < ctlr->msg_num) {
275 cur_msg = ctlr->msgs + ctlr->msg_tx_idx;
276 last_msg = (ctlr->msg_tx_idx == ctlr->msg_num - 1);
279 if (ctlr->msg_tx_idx && !ctlr->buf_tx_idx)
282 fifo_state = readl(ctlr->iobase + HISI_I2C_FIFO_STATE);
284 ctlr->buf_tx_idx < cur_msg->len && max_write) {
293 if (ctlr->buf_tx_idx == cur_msg->len - 1 && last_msg)
300 cur_msg->buf[ctlr->buf_tx_idx]);
302 writel(cmd, ctlr->iobase + HISI_I2C_CMD_TXDATA);
303 ctlr->buf_tx_idx++;
306 fifo_state = readl(ctlr->iobase + HISI_I2C_FIFO_STATE);
310 if (ctlr->buf_tx_idx == cur_msg->len) {
311 ctlr->buf_tx_idx = 0;
312 ctlr->msg_tx_idx++;
324 if (ctlr->msg_tx_idx == ctlr->msg_num)
325 hisi_i2c_disable_int(ctlr, HISI_I2C_INT_TX_EMPTY);
330 struct hisi_i2c_controller *ctlr = context;
338 if (!ctlr->completion)
341 int_stat = readl(ctlr->iobase + HISI_I2C_INT_MSTAT);
342 hisi_i2c_clear_int(ctlr, int_stat);
347 hisi_i2c_xfer_msg(ctlr);
350 ctlr->xfer_err = int_stat;
356 hisi_i2c_read_rx_fifo(ctlr);
364 hisi_i2c_disable_int(ctlr, HISI_I2C_INT_ALL);
365 hisi_i2c_clear_int(ctlr, HISI_I2C_INT_ALL);
366 complete(ctlr->completion);
378 static void hisi_i2c_set_scl(struct hisi_i2c_controller *ctlr,
386 total_cnt = DIV_ROUND_UP_ULL(ctlr->clk_rate_khz * HZ_PER_KHZ, ctlr->t.bus_freq_hz);
392 scl_fall_cnt = NSEC_TO_CYCLES(ctlr->t.scl_fall_ns, ctlr->clk_rate_khz);
394 scl_rise_cnt = NSEC_TO_CYCLES(ctlr->t.scl_rise_ns, ctlr->clk_rate_khz);
397 scl_hcnt = t_scl_hcnt - ctlr->spk_len - 7 - scl_fall_cnt;
400 writel(scl_hcnt, ctlr->iobase + reg_hcnt);
401 writel(scl_lcnt, ctlr->iobase + reg_lcnt);
404 static void hisi_i2c_configure_bus(struct hisi_i2c_controller *ctlr)
408 i2c_parse_fw_timings(ctlr->dev, &ctlr->t, true);
409 ctlr->spk_len = NSEC_TO_CYCLES(ctlr->t.digital_filter_width_ns, ctlr->clk_rate_khz);
411 switch (ctlr->t.bus_freq_hz) {
414 hisi_i2c_set_scl(ctlr, 26, 76, HISI_I2C_FS_SCL_HCNT, HISI_I2C_FS_SCL_LCNT);
418 hisi_i2c_set_scl(ctlr, 6, 22, HISI_I2C_HS_SCL_HCNT, HISI_I2C_HS_SCL_LCNT);
425 ctlr->t.bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ;
426 hisi_i2c_set_scl(ctlr, 40, 87, HISI_I2C_SS_SCL_HCNT, HISI_I2C_SS_SCL_LCNT);
430 reg = readl(ctlr->iobase + HISI_I2C_FRAME_CTRL);
433 writel(reg, ctlr->iobase + HISI_I2C_FRAME_CTRL);
435 sda_hold_cnt = NSEC_TO_CYCLES(ctlr->t.sda_hold_ns, ctlr->clk_rate_khz);
438 writel(reg, ctlr->iobase + HISI_I2C_SDA_HOLD);
440 writel(ctlr->spk_len, ctlr->iobase + HISI_I2C_FS_SPK_LEN);
444 writel(reg, ctlr->iobase + HISI_I2C_FIFO_CTRL);
449 struct hisi_i2c_controller *ctlr;
456 ctlr = devm_kzalloc(dev, sizeof(*ctlr), GFP_KERNEL);
457 if (!ctlr)
460 ctlr->iobase = devm_platform_ioremap_resource(pdev, 0);
461 if (IS_ERR(ctlr->iobase))
462 return PTR_ERR(ctlr->iobase);
464 ctlr->irq = platform_get_irq(pdev, 0);
465 if (ctlr->irq < 0)
466 return ctlr->irq;
468 ctlr->dev = dev;
470 hisi_i2c_disable_int(ctlr, HISI_I2C_INT_ALL);
472 ret = devm_request_irq(dev, ctlr->irq, hisi_i2c_irq, 0, "hisi-i2c", ctlr);
476 ctlr->clk = devm_clk_get_optional_enabled(&pdev->dev, NULL);
477 if (IS_ERR_OR_NULL(ctlr->clk)) {
482 clk_rate_hz = clk_get_rate(ctlr->clk);
485 ctlr->clk_rate_khz = DIV_ROUND_UP_ULL(clk_rate_hz, HZ_PER_KHZ);
487 hisi_i2c_configure_bus(ctlr);
489 adapter = &ctlr->adapter;
495 i2c_set_adapdata(adapter, ctlr);
501 hw_version = readl(ctlr->iobase + HISI_I2C_VERSION);
502 dev_info(ctlr->dev, "speed mode is %s. hw version 0x%x\n",
503 i2c_freq_mode_string(ctlr->t.bus_freq_hz), hw_version);