Lines Matching defs:i2c
3 * i2c-exynos5.c - Samsung Exynos5 I2C Controller Driver
11 #include <linux/i2c.h>
258 static void exynos5_i2c_clr_pend_irq(struct exynos5_i2c *i2c)
260 writel(readl(i2c->regs + HSI2C_INT_STATUS),
261 i2c->regs + HSI2C_INT_STATUS);
274 static int exynos5_i2c_set_timing(struct exynos5_i2c *i2c, bool hs_timings)
286 unsigned int clkin = clk_get_rate(i2c->clk);
287 unsigned int op_clk = hs_timings ? i2c->op_clock :
288 (i2c->op_clock >= I2C_MAX_FAST_MODE_PLUS_FREQ) ? I2C_MAX_STANDARD_MODE_FREQ :
289 i2c->op_clock;
306 if (i2c->variant->hw == I2C_TYPE_EXYNOSAUTOV9) {
307 div = ((clkin / (16 * i2c->op_clock)) - 1);
310 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_HS3);
312 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_FS3);
332 t_ftl_cycle = (readl(i2c->regs + HSI2C_CONF) >> 16) & 0x7;
334 if (i2c->variant->hw != I2C_TYPE_EXYNOS7)
339 dev_err(i2c->dev, "%s clock set-up failed\n",
358 dev_dbg(i2c->dev, "tSTART_SU: %X, tSTART_HD: %X, tSTOP_SU: %X\n",
360 dev_dbg(i2c->dev, "tDATA_SU: %X, tSCL_L: %X, tSCL_H: %X\n",
362 dev_dbg(i2c->dev, "nClkDiv: %X, tSR_RELEASE: %X\n",
364 dev_dbg(i2c->dev, "tDATA_HD: %X\n", t_data_hd);
367 writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_HS1);
368 writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_HS2);
369 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_HS3);
371 writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_FS1);
372 writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_FS2);
373 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_FS3);
375 writel(i2c_timing_sla, i2c->regs + HSI2C_TIMING_SLA);
380 static int exynos5_hsi2c_clock_setup(struct exynos5_i2c *i2c)
383 int ret = exynos5_i2c_set_timing(i2c, false);
385 if (ret < 0 || i2c->op_clock < I2C_MAX_FAST_MODE_PLUS_FREQ)
388 return exynos5_i2c_set_timing(i2c, true);
395 static void exynos5_i2c_init(struct exynos5_i2c *i2c)
397 u32 i2c_conf = readl(i2c->regs + HSI2C_CONF);
398 u32 i2c_timeout = readl(i2c->regs + HSI2C_TIMEOUT);
402 writel(i2c_timeout, i2c->regs + HSI2C_TIMEOUT);
405 i2c->regs + HSI2C_CTL);
406 writel(HSI2C_TRAILING_COUNT, i2c->regs + HSI2C_TRAILIG_CTL);
408 if (i2c->op_clock >= I2C_MAX_FAST_MODE_PLUS_FREQ) {
409 writel(HSI2C_MASTER_ID(MASTER_ID(i2c->adap.nr)),
410 i2c->regs + HSI2C_ADDR);
414 writel(i2c_conf | HSI2C_AUTO_MODE, i2c->regs + HSI2C_CONF);
417 static void exynos5_i2c_reset(struct exynos5_i2c *i2c)
422 i2c_ctl = readl(i2c->regs + HSI2C_CTL);
424 writel(i2c_ctl, i2c->regs + HSI2C_CTL);
426 i2c_ctl = readl(i2c->regs + HSI2C_CTL);
428 writel(i2c_ctl, i2c->regs + HSI2C_CTL);
431 exynos5_hsi2c_clock_setup(i2c);
433 exynos5_i2c_init(i2c);
445 struct exynos5_i2c *i2c = dev_id;
450 i2c->state = -EINVAL;
452 spin_lock(&i2c->lock);
454 int_status = readl(i2c->regs + HSI2C_INT_STATUS);
455 writel(int_status, i2c->regs + HSI2C_INT_STATUS);
458 switch (i2c->variant->hw) {
463 i2c->trans_done = 1;
464 i2c->state = 0;
466 dev_dbg(i2c->dev, "Deal with arbitration lose\n");
467 i2c->state = -EAGAIN;
470 dev_dbg(i2c->dev, "No ACK from device\n");
471 i2c->state = -ENXIO;
474 dev_dbg(i2c->dev, "No device\n");
475 i2c->state = -ENXIO;
478 dev_dbg(i2c->dev, "Accessing device timed out\n");
479 i2c->state = -ETIMEDOUT;
488 trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS);
490 dev_dbg(i2c->dev, "No ACK from device\n");
491 i2c->state = -ENXIO;
494 dev_dbg(i2c->dev, "No device\n");
495 i2c->state = -ENXIO;
498 dev_dbg(i2c->dev, "Deal with arbitration lose\n");
499 i2c->state = -EAGAIN;
502 dev_dbg(i2c->dev, "Accessing device timed out\n");
503 i2c->state = -ETIMEDOUT;
506 i2c->trans_done = 1;
507 i2c->state = 0;
513 if ((i2c->msg->flags & I2C_M_RD) && (int_status &
515 fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS);
517 len = min(fifo_level, i2c->msg->len - i2c->msg_ptr);
521 readl(i2c->regs + HSI2C_RX_DATA);
522 i2c->msg->buf[i2c->msg_ptr++] = byte;
525 i2c->state = 0;
527 fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS);
530 len = i2c->variant->fifo_depth - fifo_level;
531 if (len > (i2c->msg->len - i2c->msg_ptr)) {
532 u32 int_en = readl(i2c->regs + HSI2C_INT_ENABLE);
535 writel(int_en, i2c->regs + HSI2C_INT_ENABLE);
536 len = i2c->msg->len - i2c->msg_ptr;
540 byte = i2c->msg->buf[i2c->msg_ptr++];
541 writel(byte, i2c->regs + HSI2C_TX_DATA);
544 i2c->state = 0;
548 if ((i2c->trans_done && (i2c->msg->len == i2c->msg_ptr)) ||
549 (i2c->state < 0)) {
550 writel(0, i2c->regs + HSI2C_INT_ENABLE);
551 exynos5_i2c_clr_pend_irq(i2c);
552 complete(&i2c->msg_complete);
555 spin_unlock(&i2c->lock);
568 static int exynos5_i2c_wait_bus_idle(struct exynos5_i2c *i2c)
576 trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS);
586 static void exynos5_i2c_bus_recover(struct exynos5_i2c *i2c)
590 val = readl(i2c->regs + HSI2C_CTL) | HSI2C_RXCHON;
591 writel(val, i2c->regs + HSI2C_CTL);
592 val = readl(i2c->regs + HSI2C_CONF) & ~HSI2C_AUTO_MODE;
593 writel(val, i2c->regs + HSI2C_CONF);
600 writel(HSI2C_CMD_READ_DATA, i2c->regs + HSI2C_MANUAL_CMD);
601 exynos5_i2c_wait_bus_idle(i2c);
602 writel(HSI2C_CMD_SEND_STOP, i2c->regs + HSI2C_MANUAL_CMD);
603 exynos5_i2c_wait_bus_idle(i2c);
605 val = readl(i2c->regs + HSI2C_CTL) & ~HSI2C_RXCHON;
606 writel(val, i2c->regs + HSI2C_CTL);
607 val = readl(i2c->regs + HSI2C_CONF) | HSI2C_AUTO_MODE;
608 writel(val, i2c->regs + HSI2C_CONF);
611 static void exynos5_i2c_bus_check(struct exynos5_i2c *i2c)
615 if (i2c->variant->hw == I2C_TYPE_EXYNOS5)
625 u32 st = readl(i2c->regs + HSI2C_TRANS_STATUS);
633 exynos5_i2c_bus_recover(i2c);
639 * i2c: struct exynos5_i2c pointer for the current bus
647 static void exynos5_i2c_message_start(struct exynos5_i2c *i2c, int stop)
657 if (i2c->variant->hw == I2C_TYPE_EXYNOS5)
662 i2c_ctl = readl(i2c->regs + HSI2C_CTL);
666 if (i2c->msg->flags & I2C_M_RD) {
671 trig_lvl = (i2c->msg->len > i2c->variant->fifo_depth) ?
672 (i2c->variant->fifo_depth * 3 / 4) : i2c->msg->len;
680 trig_lvl = (i2c->msg->len > i2c->variant->fifo_depth) ?
681 (i2c->variant->fifo_depth * 1 / 4) : i2c->msg->len;
687 i2c_addr = HSI2C_SLV_ADDR_MAS(i2c->msg->addr);
689 if (i2c->op_clock >= I2C_MAX_FAST_MODE_PLUS_FREQ)
690 i2c_addr |= HSI2C_MASTER_ID(MASTER_ID(i2c->adap.nr));
692 writel(i2c_addr, i2c->regs + HSI2C_ADDR);
694 writel(fifo_ctl, i2c->regs + HSI2C_FIFO_CTL);
695 writel(i2c_ctl, i2c->regs + HSI2C_CTL);
697 exynos5_i2c_bus_check(i2c);
703 spin_lock_irqsave(&i2c->lock, flags);
704 writel(int_en, i2c->regs + HSI2C_INT_ENABLE);
708 i2c_auto_conf |= i2c->msg->len;
710 writel(i2c_auto_conf, i2c->regs + HSI2C_AUTO_CONF);
711 spin_unlock_irqrestore(&i2c->lock, flags);
714 static int exynos5_i2c_xfer_msg(struct exynos5_i2c *i2c,
720 i2c->msg = msgs;
721 i2c->msg_ptr = 0;
722 i2c->trans_done = 0;
724 reinit_completion(&i2c->msg_complete);
726 exynos5_i2c_message_start(i2c, stop);
728 timeout = wait_for_completion_timeout(&i2c->msg_complete,
733 ret = i2c->state;
740 ret = exynos5_i2c_wait_bus_idle(i2c);
743 exynos5_i2c_reset(i2c);
745 dev_warn(i2c->dev, "%s timeout\n",
756 struct exynos5_i2c *i2c = adap->algo_data;
759 ret = clk_enable(i2c->pclk);
763 ret = clk_enable(i2c->clk);
768 ret = exynos5_i2c_xfer_msg(i2c, msgs + i, i + 1 == num);
773 clk_disable(i2c->clk);
775 clk_disable(i2c->pclk);
793 struct exynos5_i2c *i2c;
796 i2c = devm_kzalloc(&pdev->dev, sizeof(struct exynos5_i2c), GFP_KERNEL);
797 if (!i2c)
800 if (of_property_read_u32(np, "clock-frequency", &i2c->op_clock))
801 i2c->op_clock = I2C_MAX_STANDARD_MODE_FREQ;
803 strscpy(i2c->adap.name, "exynos5-i2c", sizeof(i2c->adap.name));
804 i2c->adap.owner = THIS_MODULE;
805 i2c->adap.algo = &exynos5_i2c_algorithm;
806 i2c->adap.retries = 3;
808 i2c->dev = &pdev->dev;
809 i2c->clk = devm_clk_get(&pdev->dev, "hsi2c");
810 if (IS_ERR(i2c->clk)) {
815 i2c->pclk = devm_clk_get_optional(&pdev->dev, "hsi2c_pclk");
816 if (IS_ERR(i2c->pclk)) {
817 return dev_err_probe(&pdev->dev, PTR_ERR(i2c->pclk),
821 ret = clk_prepare_enable(i2c->pclk);
825 ret = clk_prepare_enable(i2c->clk);
829 i2c->regs = devm_platform_ioremap_resource(pdev, 0);
830 if (IS_ERR(i2c->regs)) {
831 ret = PTR_ERR(i2c->regs);
835 i2c->adap.dev.of_node = np;
836 i2c->adap.algo_data = i2c;
837 i2c->adap.dev.parent = &pdev->dev;
840 exynos5_i2c_clr_pend_irq(i2c);
842 spin_lock_init(&i2c->lock);
843 init_completion(&i2c->msg_complete);
845 i2c->irq = ret = platform_get_irq(pdev, 0);
849 ret = devm_request_irq(&pdev->dev, i2c->irq, exynos5_i2c_irq,
850 IRQF_NO_SUSPEND, dev_name(&pdev->dev), i2c);
852 dev_err(&pdev->dev, "cannot request HS-I2C IRQ %d\n", i2c->irq);
856 i2c->variant = of_device_get_match_data(&pdev->dev);
858 ret = exynos5_hsi2c_clock_setup(i2c);
862 exynos5_i2c_reset(i2c);
864 ret = i2c_add_adapter(&i2c->adap);
868 platform_set_drvdata(pdev, i2c);
870 clk_disable(i2c->clk);
871 clk_disable(i2c->pclk);
876 clk_disable_unprepare(i2c->clk);
879 clk_disable_unprepare(i2c->pclk);
885 struct exynos5_i2c *i2c = platform_get_drvdata(pdev);
887 i2c_del_adapter(&i2c->adap);
889 clk_unprepare(i2c->clk);
890 clk_unprepare(i2c->pclk);
895 struct exynos5_i2c *i2c = dev_get_drvdata(dev);
897 i2c_mark_adapter_suspended(&i2c->adap);
898 clk_unprepare(i2c->clk);
899 clk_unprepare(i2c->pclk);
906 struct exynos5_i2c *i2c = dev_get_drvdata(dev);
909 ret = clk_prepare_enable(i2c->pclk);
913 ret = clk_prepare_enable(i2c->clk);
917 ret = exynos5_hsi2c_clock_setup(i2c);
921 exynos5_i2c_init(i2c);
922 clk_disable(i2c->clk);
923 clk_disable(i2c->pclk);
924 i2c_mark_adapter_resumed(&i2c->adap);
929 clk_disable_unprepare(i2c->clk);
931 clk_disable_unprepare(i2c->pclk);