Lines Matching refs:dev
31 static void i2c_dw_configure_fifo_master(struct dw_i2c_dev *dev)
34 regmap_write(dev->map, DW_IC_TX_TL, dev->tx_fifo_depth / 2);
35 regmap_write(dev->map, DW_IC_RX_TL, 0);
38 regmap_write(dev->map, DW_IC_CON, dev->master_cfg);
41 static int i2c_dw_set_timings_master(struct dw_i2c_dev *dev)
45 struct i2c_timings *t = &dev->timings;
50 ret = i2c_dw_acquire_lock(dev);
54 ret = regmap_read(dev->map, DW_IC_COMP_PARAM_1, &comp_param1);
55 i2c_dw_release_lock(dev);
64 if (!dev->ss_hcnt || !dev->ss_lcnt) {
65 ic_clk = i2c_dw_clk_rate(dev);
66 dev->ss_hcnt =
72 dev->ss_lcnt =
78 dev_dbg(dev->dev, "Standard Mode HCNT:LCNT = %d:%d\n",
79 dev->ss_hcnt, dev->ss_lcnt);
91 if (dev->fp_hcnt && dev->fp_lcnt) {
92 dev->fs_hcnt = dev->fp_hcnt;
93 dev->fs_lcnt = dev->fp_lcnt;
95 ic_clk = i2c_dw_clk_rate(dev);
96 dev->fs_hcnt =
102 dev->fs_lcnt =
114 if (!dev->fs_hcnt || !dev->fs_lcnt) {
115 ic_clk = i2c_dw_clk_rate(dev);
116 dev->fs_hcnt =
122 dev->fs_lcnt =
128 dev_dbg(dev->dev, "Fast Mode%s HCNT:LCNT = %d:%d\n",
129 fp_str, dev->fs_hcnt, dev->fs_lcnt);
132 if ((dev->master_cfg & DW_IC_CON_SPEED_MASK) ==
136 dev_err(dev->dev, "High Speed not supported!\n");
138 dev->master_cfg &= ~DW_IC_CON_SPEED_MASK;
139 dev->master_cfg |= DW_IC_CON_SPEED_FAST;
140 dev->hs_hcnt = 0;
141 dev->hs_lcnt = 0;
142 } else if (!dev->hs_hcnt || !dev->hs_lcnt) {
143 ic_clk = i2c_dw_clk_rate(dev);
144 dev->hs_hcnt =
150 dev->hs_lcnt =
156 dev_dbg(dev->dev, "High Speed Mode HCNT:LCNT = %d:%d\n",
157 dev->hs_hcnt, dev->hs_lcnt);
160 ret = i2c_dw_set_sda_hold(dev);
164 dev_dbg(dev->dev, "Bus speed: %s\n", i2c_freq_mode_string(t->bus_freq_hz));
170 * @dev: device private data
176 static int i2c_dw_init_master(struct dw_i2c_dev *dev)
180 ret = i2c_dw_acquire_lock(dev);
185 __i2c_dw_disable(dev);
188 regmap_write(dev->map, DW_IC_SS_SCL_HCNT, dev->ss_hcnt);
189 regmap_write(dev->map, DW_IC_SS_SCL_LCNT, dev->ss_lcnt);
192 regmap_write(dev->map, DW_IC_FS_SCL_HCNT, dev->fs_hcnt);
193 regmap_write(dev->map, DW_IC_FS_SCL_LCNT, dev->fs_lcnt);
196 if (dev->hs_hcnt && dev->hs_lcnt) {
197 regmap_write(dev->map, DW_IC_HS_SCL_HCNT, dev->hs_hcnt);
198 regmap_write(dev->map, DW_IC_HS_SCL_LCNT, dev->hs_lcnt);
202 if (dev->sda_hold_time)
203 regmap_write(dev->map, DW_IC_SDA_HOLD, dev->sda_hold_time);
205 i2c_dw_configure_fifo_master(dev);
206 i2c_dw_release_lock(dev);
211 static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
213 struct i2c_msg *msgs = dev->msgs;
218 __i2c_dw_disable(dev);
221 if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) {
232 regmap_update_bits(dev->map, DW_IC_CON, DW_IC_CON_10BITADDR_MASTER,
239 regmap_write(dev->map, DW_IC_TAR,
240 msgs[dev->msg_write_idx].addr | ic_tar);
243 regmap_write(dev->map, DW_IC_INTR_MASK, 0);
246 __i2c_dw_enable(dev);
249 regmap_read(dev->map, DW_IC_ENABLE_STATUS, &dummy);
252 regmap_read(dev->map, DW_IC_CLR_INTR, &dummy);
253 regmap_write(dev->map, DW_IC_INTR_MASK, DW_IC_INTR_MASTER_MASK);
256 static int i2c_dw_check_stopbit(struct dw_i2c_dev *dev)
261 ret = regmap_read_poll_timeout(dev->map, DW_IC_INTR_STAT, val,
265 dev_err(dev->dev, "i2c timeout error %d\n", ret);
270 static int i2c_dw_status(struct dw_i2c_dev *dev)
274 status = i2c_dw_wait_bus_not_busy(dev);
278 return i2c_dw_check_stopbit(dev);
287 struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
298 regmap_write(dev->map, AMD_UCSI_INTR_REG, AMD_UCSI_INTR_EN);
300 dev->msgs = msgs;
301 dev->msgs_num = num_msgs;
302 i2c_dw_xfer_init(dev);
303 regmap_write(dev->map, DW_IC_INTR_MASK, 0);
311 regmap_write(dev->map, DW_IC_TX_TL, buf_len - 1);
323 regmap_write(dev->map, DW_IC_DATA_CMD, 0x100);
324 regmap_write(dev->map, DW_IC_DATA_CMD, 0x100 | cmd);
326 regmap_write(dev->map, DW_IC_TX_TL, 2 * (buf_len - 1));
327 regmap_write(dev->map, DW_IC_RX_TL, 2 * (buf_len - 1));
333 status = i2c_dw_status(dev);
338 regmap_read(dev->map, DW_IC_DATA_CMD, &val);
341 status = i2c_dw_check_stopbit(dev);
346 regmap_write(dev->map, DW_IC_DATA_CMD, *tx_buf++ | cmd);
350 status = i2c_dw_check_stopbit(dev);
358 static int i2c_dw_poll_tx_empty(struct dw_i2c_dev *dev)
362 return regmap_read_poll_timeout(dev->map, DW_IC_RAW_INTR_STAT, val,
367 static int i2c_dw_poll_rx_full(struct dw_i2c_dev *dev)
371 return regmap_read_poll_timeout(dev->map, DW_IC_RAW_INTR_STAT, val,
379 struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
384 dev->msgs = msgs;
385 dev->msgs_num = num_msgs;
386 i2c_dw_xfer_init(dev);
387 regmap_write(dev->map, DW_IC_INTR_MASK, 0);
398 regmap_write(dev->map, DW_IC_DATA_CMD, 0x100 | stop);
400 ret = i2c_dw_poll_rx_full(dev);
404 regmap_read(dev->map, DW_IC_DATA_CMD, &val);
407 ret = i2c_dw_poll_tx_empty(dev);
411 regmap_write(dev->map, DW_IC_DATA_CMD,
427 i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
429 struct i2c_msg *msgs = dev->msgs;
432 u32 addr = msgs[dev->msg_write_idx].addr;
433 u32 buf_len = dev->tx_buf_len;
434 u8 *buf = dev->tx_buf;
440 for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) {
441 u32 flags = msgs[dev->msg_write_idx].flags;
448 if (msgs[dev->msg_write_idx].addr != addr) {
449 dev_err(dev->dev,
451 dev->msg_err = -EINVAL;
455 if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) {
457 buf = msgs[dev->msg_write_idx].buf;
458 buf_len = msgs[dev->msg_write_idx].len;
464 if ((dev->master_cfg & DW_IC_CON_RESTART_EN) &&
465 (dev->msg_write_idx > 0))
469 regmap_read(dev->map, DW_IC_TXFLR, &flr);
470 tx_limit = dev->tx_fifo_depth - flr;
472 regmap_read(dev->map, DW_IC_RXFLR, &flr);
473 rx_limit = dev->rx_fifo_depth - flr;
491 if (dev->msg_write_idx == dev->msgs_num - 1 &&
500 if (msgs[dev->msg_write_idx].flags & I2C_M_RD) {
503 if (dev->rx_outstanding >= dev->rx_fifo_depth)
506 regmap_write(dev->map, DW_IC_DATA_CMD,
509 dev->rx_outstanding++;
511 regmap_write(dev->map, DW_IC_DATA_CMD,
517 dev->tx_buf = buf;
518 dev->tx_buf_len = buf_len;
528 dev->status |= STATUS_WRITE_IN_PROGRESS;
533 dev->status |= STATUS_WRITE_IN_PROGRESS;
536 dev->status &= ~STATUS_WRITE_IN_PROGRESS;
543 if (dev->msg_write_idx == dev->msgs_num)
546 if (dev->msg_err)
549 regmap_write(dev->map, DW_IC_INTR_MASK, intr_mask);
553 i2c_dw_recv_len(struct dw_i2c_dev *dev, u8 len)
555 struct i2c_msg *msgs = dev->msgs;
556 u32 flags = msgs[dev->msg_read_idx].flags;
563 dev->tx_buf_len = len - min_t(u8, len, dev->rx_outstanding);
564 msgs[dev->msg_read_idx].len = len;
565 msgs[dev->msg_read_idx].flags &= ~I2C_M_RECV_LEN;
571 regmap_update_bits(dev->map, DW_IC_INTR_MASK, DW_IC_INTR_TX_EMPTY,
578 i2c_dw_read(struct dw_i2c_dev *dev)
580 struct i2c_msg *msgs = dev->msgs;
583 for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) {
588 if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD))
591 if (!(dev->status & STATUS_READ_IN_PROGRESS)) {
592 len = msgs[dev->msg_read_idx].len;
593 buf = msgs[dev->msg_read_idx].buf;
595 len = dev->rx_buf_len;
596 buf = dev->rx_buf;
599 regmap_read(dev->map, DW_IC_RXFLR, &rx_valid);
602 u32 flags = msgs[dev->msg_read_idx].flags;
604 regmap_read(dev->map, DW_IC_DATA_CMD, &tmp);
620 len = i2c_dw_recv_len(dev, tmp);
623 dev->rx_outstanding--;
627 dev->status |= STATUS_READ_IN_PROGRESS;
628 dev->rx_buf_len = len;
629 dev->rx_buf = buf;
632 dev->status &= ~STATUS_READ_IN_PROGRESS;
642 struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
645 dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
647 pm_runtime_get_sync(dev->dev);
654 switch (dev->flags & MODEL_MASK) {
665 reinit_completion(&dev->cmd_complete);
666 dev->msgs = msgs;
667 dev->msgs_num = num;
668 dev->cmd_err = 0;
669 dev->msg_write_idx = 0;
670 dev->msg_read_idx = 0;
671 dev->msg_err = 0;
672 dev->status = 0;
673 dev->abort_source = 0;
674 dev->rx_outstanding = 0;
676 ret = i2c_dw_acquire_lock(dev);
680 ret = i2c_dw_wait_bus_not_busy(dev);
685 i2c_dw_xfer_init(dev);
688 if (!wait_for_completion_timeout(&dev->cmd_complete, adap->timeout)) {
689 dev_err(dev->dev, "controller timed out\n");
691 i2c_recover_bus(&dev->adapter);
692 i2c_dw_init_master(dev);
705 __i2c_dw_disable_nowait(dev);
707 if (dev->msg_err) {
708 ret = dev->msg_err;
713 if (likely(!dev->cmd_err && !dev->status)) {
719 if (dev->cmd_err == DW_IC_ERR_TX_ABRT) {
720 ret = i2c_dw_handle_tx_abort(dev);
724 if (dev->status)
725 dev_err(dev->dev,
731 i2c_dw_release_lock(dev);
734 pm_runtime_mark_last_busy(dev->dev);
735 pm_runtime_put_autosuspend(dev->dev);
749 static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev)
765 regmap_read(dev->map, DW_IC_INTR_STAT, &stat);
775 regmap_read(dev->map, DW_IC_CLR_RX_UNDER, &dummy);
777 regmap_read(dev->map, DW_IC_CLR_RX_OVER, &dummy);
779 regmap_read(dev->map, DW_IC_CLR_TX_OVER, &dummy);
781 regmap_read(dev->map, DW_IC_CLR_RD_REQ, &dummy);
787 regmap_read(dev->map, DW_IC_TX_ABRT_SOURCE, &dev->abort_source);
788 regmap_read(dev->map, DW_IC_CLR_TX_ABRT, &dummy);
791 regmap_read(dev->map, DW_IC_CLR_RX_DONE, &dummy);
793 regmap_read(dev->map, DW_IC_CLR_ACTIVITY, &dummy);
795 ((dev->rx_outstanding == 0) || (stat & DW_IC_INTR_RX_FULL)))
796 regmap_read(dev->map, DW_IC_CLR_STOP_DET, &dummy);
798 regmap_read(dev->map, DW_IC_CLR_START_DET, &dummy);
800 regmap_read(dev->map, DW_IC_CLR_GEN_CALL, &dummy);
811 struct dw_i2c_dev *dev = dev_id;
814 regmap_read(dev->map, DW_IC_ENABLE, &enabled);
815 regmap_read(dev->map, DW_IC_RAW_INTR_STAT, &stat);
818 if (pm_runtime_suspended(dev->dev) || stat == GENMASK(31, 0))
820 dev_dbg(dev->dev, "enabled=%#x stat=%#x\n", enabled, stat);
822 stat = i2c_dw_read_clear_intrbits(dev);
824 if (!(dev->status & STATUS_ACTIVE)) {
832 regmap_write(dev->map, DW_IC_INTR_MASK, 0);
837 dev->cmd_err |= DW_IC_ERR_TX_ABRT;
838 dev->status &= ~STATUS_MASK;
839 dev->rx_outstanding = 0;
845 regmap_write(dev->map, DW_IC_INTR_MASK, 0);
850 i2c_dw_read(dev);
853 i2c_dw_xfer_msg(dev);
862 if (((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err) &&
863 (dev->rx_outstanding == 0))
864 complete(&dev->cmd_complete);
865 else if (unlikely(dev->flags & ACCESS_INTR_MASK)) {
867 regmap_read(dev->map, DW_IC_INTR_MASK, &stat);
868 regmap_write(dev->map, DW_IC_INTR_MASK, 0);
869 regmap_write(dev->map, DW_IC_INTR_MASK, stat);
875 void i2c_dw_configure_master(struct dw_i2c_dev *dev)
877 struct i2c_timings *t = &dev->timings;
879 dev->functionality = I2C_FUNC_10BIT_ADDR | DW_IC_DEFAULT_FUNCTIONALITY;
881 dev->master_cfg = DW_IC_CON_MASTER | DW_IC_CON_SLAVE_DISABLE |
884 dev->mode = DW_IC_MASTER;
888 dev->master_cfg |= DW_IC_CON_SPEED_STD;
891 dev->master_cfg |= DW_IC_CON_SPEED_HIGH;
894 dev->master_cfg |= DW_IC_CON_SPEED_FAST;
901 struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
903 i2c_dw_disable(dev);
904 reset_control_assert(dev->rst);
905 i2c_dw_prepare_clk(dev, false);
910 struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
912 i2c_dw_prepare_clk(dev, true);
913 reset_control_deassert(dev->rst);
914 i2c_dw_init_master(dev);
917 static int i2c_dw_init_recovery_info(struct dw_i2c_dev *dev)
919 struct i2c_bus_recovery_info *rinfo = &dev->rinfo;
920 struct i2c_adapter *adap = &dev->adapter;
923 gpio = devm_gpiod_get_optional(dev->dev, "scl", GPIOD_OUT_HIGH);
929 gpio = devm_gpiod_get_optional(dev->dev, "sda", GPIOD_IN);
934 rinfo->pinctrl = devm_pinctrl_get(dev->dev);
940 dev_err(dev->dev, "getting pinctrl info failed: bus recovery might not work\n");
942 dev_dbg(dev->dev, "pinctrl is disabled, bus recovery might not work\n");
950 dev_info(dev->dev, "running with gpio recovery mode! scl%s",
956 static int i2c_dw_poll_adap_quirk(struct dw_i2c_dev *dev)
958 struct i2c_adapter *adap = &dev->adapter;
961 pm_runtime_get_noresume(dev->dev);
964 dev_err(dev->dev, "Failed to add adapter: %d\n", ret);
965 pm_runtime_put_noidle(dev->dev);
970 static bool i2c_dw_is_model_poll(struct dw_i2c_dev *dev)
972 switch (dev->flags & MODEL_MASK) {
981 int i2c_dw_probe_master(struct dw_i2c_dev *dev)
983 struct i2c_adapter *adap = &dev->adapter;
988 init_completion(&dev->cmd_complete);
990 dev->init = i2c_dw_init_master;
991 dev->disable = i2c_dw_disable;
993 ret = i2c_dw_init_regmap(dev);
997 ret = i2c_dw_set_timings_master(dev);
1001 ret = i2c_dw_set_fifo_size(dev);
1006 ret = i2c_dw_acquire_lock(dev);
1016 ret = regmap_read(dev->map, DW_IC_CON, &ic_con);
1017 i2c_dw_release_lock(dev);
1022 dev->master_cfg |= DW_IC_CON_BUS_CLEAR_CTRL;
1024 ret = dev->init(dev);
1033 adap->dev.parent = dev->dev;
1034 i2c_set_adapdata(adap, dev);
1036 if (i2c_dw_is_model_poll(dev))
1037 return i2c_dw_poll_adap_quirk(dev);
1039 if (dev->flags & ACCESS_NO_IRQ_SUSPEND) {
1045 ret = i2c_dw_acquire_lock(dev);
1049 regmap_write(dev->map, DW_IC_INTR_MASK, 0);
1050 i2c_dw_release_lock(dev);
1052 ret = devm_request_irq(dev->dev, dev->irq, i2c_dw_isr, irq_flags,
1053 dev_name(dev->dev), dev);
1055 dev_err(dev->dev, "failure requesting irq %i: %d\n",
1056 dev->irq, ret);
1060 ret = i2c_dw_init_recovery_info(dev);
1070 pm_runtime_get_noresume(dev->dev);
1073 dev_err(dev->dev, "failure adding adapter: %d\n", ret);
1074 pm_runtime_put_noidle(dev->dev);