Lines Matching defs:clk_low
828 u32 base_clk_divisor, clk_high_low_max, clk_high, clk_low, tmp;
851 * SCL_low = clk_low + 1
854 * ((1 << base_clk_divisor) * (clk_high + 1 + clk_low + 1))
856 * clk_low >= clk_low_max / 2 - 1 when possible; this last constraint
864 clk_low = clk_high_low_mask;
872 clk_low = tmp / 2;
873 clk_high = tmp - clk_low;
878 if (clk_low)
879 clk_low--;
885 | ((clk_low << ASPEED_I2CD_TIME_SCL_LOW_SHIFT)
894 * clk_high and clk_low are each 3 bits wide, so each can hold a max
903 * clk_high and clk_low are each 4 bits wide, so each can hold a max