Lines Matching defs:clk_high
828 u32 base_clk_divisor, clk_high_low_max, clk_high, clk_low, tmp;
850 * SCL_high = clk_high + 1
854 * ((1 << base_clk_divisor) * (clk_high + 1 + clk_low + 1))
855 * The documentation recommends clk_high >= clk_high_max / 2 and
865 clk_high = clk_high_low_mask;
873 clk_high = tmp - clk_low;
875 if (clk_high)
876 clk_high--;
883 return ((clk_high << ASPEED_I2CD_TIME_SCL_HIGH_SHIFT)
894 * clk_high and clk_low are each 3 bits wide, so each can hold a max
903 * clk_high and clk_low are each 4 bits wide, so each can hold a max