Lines Matching defs:w83627ehf_write_value
421 static int w83627ehf_write_value(struct w83627ehf_data *data, u16 reg,
458 return w83627ehf_write_value(data, reg, value);
472 w83627ehf_write_value(data, W83627EHF_REG_FANDIV1, reg);
475 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
482 w83627ehf_write_value(data, W83627EHF_REG_FANDIV1, reg);
485 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
490 w83627ehf_write_value(data, W83627EHF_REG_FANDIV2, reg);
493 w83627ehf_write_value(data, W83627EHF_REG_VBAT, reg);
498 w83627ehf_write_value(data, W83627EHF_REG_DIODE, reg);
501 w83627ehf_write_value(data, W83627EHF_REG_SMI_OVT, reg);
507 w83627ehf_write_value(data, W83627EHF_REG_DIODE, reg);
618 w83627ehf_write_value(data,
707 w83627ehf_write_value(data, W83627EHF_REG_IN_##REG(channel), \
781 w83627ehf_write_value(data, W83627EHF_REG_FAN_MIN[channel],
810 w83627ehf_write_value(data, W83627EHF_REG_TEMP_OFFSET[channel], val);
830 w83627ehf_write_value(data, W83627EHF_REG_PWM_ENABLE[channel], reg);
843 w83627ehf_write_value(data, W83627EHF_REG_PWM[channel], val);
864 w83627ehf_write_value(data, W83627EHF_REG_PWM_ENABLE[channel],
902 w83627ehf_write_value(data, W83627EHF_REG_TARGET[nr], val);
931 w83627ehf_write_value(data, W83627EHF_REG_TOLERANCE[nr], reg);
983 w83627ehf_write_value(data, REG[nr], val); \
1022 w83627ehf_write_value(data, REG[nr], val); \
1100 w83627ehf_write_value(data, W83627EHF_REG_CASEOPEN_CLR, reg | mask);
1101 w83627ehf_write_value(data, W83627EHF_REG_CASEOPEN_CLR, reg & ~mask);
1226 w83627ehf_write_value(data, W83627EHF_REG_CONFIG,
1238 w83627ehf_write_value(data,
1246 w83627ehf_write_value(data, W83627EHF_REG_VBAT, tmp | 0x01);
1971 w83627ehf_write_value(data, W83627EHF_REG_IN_MIN(i),
1973 w83627ehf_write_value(data, W83627EHF_REG_IN_MAX(i),
1981 w83627ehf_write_value(data, W83627EHF_REG_FAN_MIN[i],
1998 w83627ehf_write_value(data,
2004 w83627ehf_write_value(data, W83627EHF_REG_VBAT, data->vbat);