Lines Matching refs:chan_rank
59 int chan_rank, u32 *data);
96 int chan_rank = dimm_no / priv->gen_info->dimm_idx_max;
104 ret = peci_pcs_read(priv->peci_dev, PECI_PCS_DDR_DIMM_TEMP, chan_rank, &data);
122 int chan_rank = dimm_no / priv->gen_info->dimm_idx_max;
129 ret = priv->gen_info->read_thresholds(priv, dimm_order, chan_rank, &data);
227 int chan_rank, dimm_idx, ret, i;
239 for (chan_rank = 0; chan_rank < chan_rank_max; chan_rank++) {
240 ret = peci_pcs_read(priv->peci_dev, PECI_PCS_DDR_DIMM_TEMP, chan_rank, &pcs);
249 bitmap_set(chan_rank_empty, chan_rank, 1);
258 bitmap_set(dimm_mask, chan_rank * dimm_idx_max + dimm_idx, 1);
425 read_thresholds_hsx(struct peci_dimmtemp *priv, int dimm_order, int chan_rank, u32 *data)
441 dev = 20 + chan_rank / 2 + chan_rank / 4;
442 func = chan_rank % 2;
453 read_thresholds_bdxd(struct peci_dimmtemp *priv, int dimm_order, int chan_rank, u32 *data)
465 dev = 10 + chan_rank / 2 * 2;
466 func = (chan_rank % 2) ? 6 : 2;
477 read_thresholds_skx(struct peci_dimmtemp *priv, int dimm_order, int chan_rank, u32 *data)
491 dev = 10 + chan_rank / 3 * 2 + (chan_rank % 3 == 2 ? 1 : 0);
492 func = chan_rank % 3 == 1 ? 6 : 2;
503 read_thresholds_icx(struct peci_dimmtemp *priv, int dimm_order, int chan_rank, u32 *data)
528 dev = 26 + chan_rank / 2;
529 offset = 0x224e0 + dimm_order * 4 + (chan_rank % 2) * 0x4000;
540 read_thresholds_spr(struct peci_dimmtemp *priv, int dimm_order, int chan_rank, u32 *data)
565 dev = 26 + chan_rank / 2;
566 offset = 0x219a8 + dimm_order * 4 + (chan_rank % 2) * 0x8000;