Lines Matching refs:val
277 static int pvt_read_temp(struct device *dev, u32 attr, int channel, long *val)
303 *val = pvt_calc_temp(pvt, nbs);
311 static int pvt_read_in(struct device *dev, u32 attr, int channel, long *val)
343 * n must be cast to long, since n and *val differ both in
351 *val = pre_scaler * (PVT_N_CONST * (long)n - PVT_R_CONST) /
361 u32 attr, int channel, long *val)
365 return pvt_read_temp(dev, attr, channel, val);
367 return pvt_read_in(dev, attr, channel, val);
399 u32 clk_synth, val;
447 val, !(val & SDIF_BUSY),
453 val = CFG0_MODE_2 | CFG0_PARALLEL_OUT | CFG0_12_BIT |
455 ret = regmap_write(t_map, SDIF_W, val);
460 val, !(val & SDIF_BUSY),
466 val = POWER_DELAY_CYCLE_256 | IP_TMR << SDIF_ADDR_SFT |
468 ret = regmap_write(t_map, SDIF_W, val);
473 val, !(val & SDIF_BUSY),
479 val = IP_RST_REL | IP_RUN_CONT | IP_AUTO |
482 ret = regmap_write(t_map, SDIF_W, val);
519 val, !(val & SDIF_BUSY),
525 val = (BIT(pvt->vm_channels.max) - 1) | VM_CH_INIT |
527 ret = regmap_write(v_map, SDIF_W, val);
532 val, !(val & SDIF_BUSY),
538 val = CFG1_VOL_MEAS_MODE | CFG1_PARALLEL_OUT |
541 ret = regmap_write(v_map, SDIF_W, val);
546 val, !(val & SDIF_BUSY),
552 val = POWER_DELAY_CYCLE_64 | IP_TMR << SDIF_ADDR_SFT |
554 ret = regmap_write(v_map, SDIF_W, val);
559 val, !(val & SDIF_BUSY),
565 val = IP_RST_REL | IP_RUN_CONT | IP_AUTO | IP_VM_MODE |
568 ret = regmap_write(v_map, SDIF_W, val);
769 u32 ts_num, vm_num, pd_num, ch_num, val, index, i;
801 ret = regmap_read(pvt->c_map, PVT_IP_CONFIG, &val);
805 ts_num = (val & TS_NUM_MSK) >> TS_NUM_SFT;
806 pd_num = (val & PD_NUM_MSK) >> PD_NUM_SFT;
807 vm_num = (val & VM_NUM_MSK) >> VM_NUM_SFT;
808 ch_num = (val & CH_NUM_MSK) >> CH_NUM_SFT;
812 val = 0;
814 val++;
816 val++;
817 if (!val)
820 pvt_info = devm_kcalloc(dev, val + 2, sizeof(*pvt_info), GFP_KERNEL);