Lines Matching refs:val
58 long val)
64 val = MAX31827_M_DGR_TO_16_BIT(val);
77 ret = regmap_write(st->regmap, reg, val);
91 ret = regmap_write(st->regmap, reg, val);
130 u32 attr, int channel, long *val)
148 *val = !!uval;
179 *val = MAX31827_16_BIT_TO_M_DGR(uval);
187 *val = MAX31827_16_BIT_TO_M_DGR(uval);
195 *val = MAX31827_16_BIT_TO_M_DGR(uval);
203 *val = FIELD_GET(MAX31827_CONFIGURATION_O_TEMP_STAT_MASK,
211 *val = MAX31827_16_BIT_TO_M_DGR(uval);
219 *val = MAX31827_16_BIT_TO_M_DGR(uval);
227 *val = FIELD_GET(MAX31827_CONFIGURATION_U_TEMP_STAT_MASK,
248 *val = 64000;
251 *val = 32000;
254 *val = 16000;
257 *val = 4000;
260 *val = 1000;
263 *val = 250;
266 *val = 125;
269 *val = 0;
284 u32 attr, int channel, long val)
293 if (val >> 1)
303 st->enable = val;
309 MAX31827_DEVICE_ENABLE(val));
316 return write_alarm_val(st, MAX31827_TH_REG, val);
319 return write_alarm_val(st, MAX31827_TH_HYST_REG, val);
322 return write_alarm_val(st, MAX31827_TL_REG, val);
325 return write_alarm_val(st, MAX31827_TL_HYST_REG, val);
336 switch (val) {
338 val = MAX31827_CNV_8_HZ;
341 val = MAX31827_CNV_4_HZ;
344 val = MAX31827_CNV_1_HZ;
347 val = MAX31827_CNV_1_DIV_4_HZ;
350 val = MAX31827_CNV_1_DIV_16_HZ;
353 val = MAX31827_CNV_1_DIV_32_HZ;
356 val = MAX31827_CNV_1_DIV_64_HZ;
362 val = FIELD_PREP(MAX31827_CONFIGURATION_CNV_RATE_MASK,
363 val);
368 val);