Lines Matching defs:sig
203 struct ipu_di_signal_cfg *sig)
205 u32 h_total = sig->mode.hactive + sig->mode.hsync_len +
206 sig->mode.hback_porch + sig->mode.hfront_porch;
207 u32 v_total = sig->mode.vactive + sig->mode.vsync_len +
208 sig->mode.vback_porch + sig->mode.vfront_porch;
220 .cnt_down = sig->mode.hsync_len * 2,
227 .cnt_down = sig->mode.vsync_len * 2,
240 .offset_count = (sig->mode.vsync_len +
241 sig->mode.vback_porch) / 2,
243 .repeat_count = sig->mode.vactive / 2,
248 .offset_count = sig->mode.hsync_len +
249 sig->mode.hback_porch,
251 .repeat_count = sig->mode.hactive,
266 struct ipu_di_signal_cfg *sig, int div)
268 u32 h_total = sig->mode.hactive + sig->mode.hsync_len +
269 sig->mode.hback_porch + sig->mode.hfront_porch;
270 u32 v_total = sig->mode.vactive + sig->mode.vsync_len +
271 sig->mode.vback_porch + sig->mode.vfront_porch;
281 .offset_count = div * sig->v_to_h_sync,
285 .cnt_down = sig->mode.hsync_len * 2,
292 .cnt_down = sig->mode.vsync_len * 2,
296 .offset_count = sig->mode.vsync_len +
297 sig->mode.vback_porch,
299 .repeat_count = sig->mode.vactive,
304 .offset_count = sig->mode.hsync_len +
305 sig->mode.hback_porch,
307 .repeat_count = sig->mode.hactive,
328 .offset_count = sig->mode.vsync_len +
329 sig->mode.vback_porch,
331 .repeat_count = sig->mode.vactive,
337 .offset_count = div * sig->v_to_h_sync + 18, /* magic value from Freescale TVE driver */
341 .cnt_down = sig->mode.hsync_len * 2,
345 .offset_count = sig->mode.hsync_len +
346 sig->mode.hback_porch,
348 .repeat_count = sig->mode.hactive,
358 .cnt_down = sig->mode.vsync_len * 2,
363 .offset_count = div * sig->v_to_h_sync + 18, /* magic value from Freescale TVE driver */
367 .cnt_down = sig->mode.hsync_len * 2,
376 .cnt_down = sig->mode.vsync_len * 2,
383 if (sig->hsync_pin == 2 && sig->vsync_pin == 3)
390 const struct ipu_di_signal_cfg *sig)
396 if (sig->clkflags & IPU_DI_CLKMODE_EXT) {
404 if (sig->clkflags & IPU_DI_CLKMODE_SYNC) {
424 clk_set_rate(clk, sig->mode.pixelclock);
427 div = DIV_ROUND_CLOSEST(in_rate, sig->mode.pixelclock);
444 div = DIV_ROUND_CLOSEST(clkrate, sig->mode.pixelclock);
448 error = rate / (sig->mode.pixelclock / 1000);
465 clk_set_rate(clk, sig->mode.pixelclock);
468 div = DIV_ROUND_CLOSEST(in_rate, sig->mode.pixelclock);
495 sig->mode.pixelclock,
561 int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig)
568 di->id, sig->mode.hactive, sig->mode.vactive);
573 sig->mode.pixelclock);
577 ipu_di_config_clock(di, sig);
592 if (sig->mode.flags & DISPLAY_FLAGS_INTERLACED) {
593 ipu_di_sync_config_interlaced(di, sig);
600 ipu_di_sync_config_noninterlaced(di, sig, div);
608 if (!(sig->hsync_pin == 2 && sig->vsync_pin == 3))
612 if (sig->mode.flags & DISPLAY_FLAGS_HSYNC_HIGH)
613 di_gen |= ipu_di_gen_polarity(sig->hsync_pin);
614 if (sig->mode.flags & DISPLAY_FLAGS_VSYNC_HIGH)
615 di_gen |= ipu_di_gen_polarity(sig->vsync_pin);
617 if (sig->clk_pol)
628 if (sig->enable_pol)
630 if (sig->data_pol)