Lines Matching defs:channel
202 struct ipuv3_channel *channel;
211 list_for_each_entry(channel, &ipu->channels, list) {
212 if (channel->num == num) {
213 channel = ERR_PTR(-EBUSY);
218 channel = kzalloc(sizeof(*channel), GFP_KERNEL);
219 if (!channel) {
220 channel = ERR_PTR(-ENOMEM);
224 channel->num = num;
225 channel->ipu = ipu;
226 list_add(&channel->list, &ipu->channels);
231 return channel;
235 void ipu_idmac_put(struct ipuv3_channel *channel)
237 struct ipu_soc *ipu = channel->ipu;
239 dev_dbg(ipu->dev, "%s %d\n", __func__, channel->num);
243 list_del(&channel->list);
244 kfree(channel);
253 * This is an undocumented feature, a write one to a channel bit in
254 * IPU_CHA_CUR_BUF and IPU_CHA_TRIPLE_CUR_BUF will reset the channel's
256 * 0 on the next channel enable (that's the theory anyway, the imx6 TRM
258 * for channel linking to work correctly, for instance video capture
260 * streaming unless this function is called for each channel before
263 static void __ipu_idmac_reset_current_buffer(struct ipuv3_channel *channel)
265 struct ipu_soc *ipu = channel->ipu;
266 unsigned int chno = channel->num;
271 void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel,
274 struct ipu_soc *ipu = channel->ipu;
280 reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num));
282 reg |= idma_mask(channel->num);
284 reg &= ~idma_mask(channel->num);
285 ipu_cm_write(ipu, reg, IPU_CHA_DB_MODE_SEL(channel->num));
287 __ipu_idmac_reset_current_buffer(channel);
317 int ipu_idmac_lock_enable(struct ipuv3_channel *channel, int num_bursts)
319 struct ipu_soc *ipu = channel->ipu;
344 * i.MX53 channel arbitration locking doesn't seem to work properly.
351 if (channel->num == idmac_lock_en_info[i].chnum)
422 int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel)
424 struct ipu_soc *ipu = channel->ipu;
425 unsigned int chno = channel->num;
431 bool ipu_idmac_buffer_is_ready(struct ipuv3_channel *channel, u32 buf_num)
433 struct ipu_soc *ipu = channel->ipu;
440 reg = ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num));
443 reg = ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num));
446 reg = ipu_cm_read(ipu, IPU_CHA_BUF2_RDY(channel->num));
451 return ((reg & idma_mask(channel->num)) != 0);
455 void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num)
457 struct ipu_soc *ipu = channel->ipu;
458 unsigned int chno = channel->num;
473 void ipu_idmac_clear_buffer(struct ipuv3_channel *channel, u32 buf_num)
475 struct ipu_soc *ipu = channel->ipu;
476 unsigned int chno = channel->num;
501 int ipu_idmac_enable_channel(struct ipuv3_channel *channel)
503 struct ipu_soc *ipu = channel->ipu;
509 val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num));
510 val |= idma_mask(channel->num);
511 ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num));
525 int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms)
527 struct ipu_soc *ipu = channel->ipu;
531 while (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(channel->num)) &
532 idma_mask(channel->num)) {
542 int ipu_idmac_disable_channel(struct ipuv3_channel *channel)
544 struct ipu_soc *ipu = channel->ipu;
550 /* Disable DMA channel(s) */
551 val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num));
552 val &= ~idma_mask(channel->num);
553 ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num));
555 __ipu_idmac_reset_current_buffer(channel);
557 /* Set channel buffers NOT to be ready */
560 if (ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num)) &
561 idma_mask(channel->num)) {
562 ipu_cm_write(ipu, idma_mask(channel->num),
563 IPU_CHA_BUF0_RDY(channel->num));
566 if (ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num)) &
567 idma_mask(channel->num)) {
568 ipu_cm_write(ipu, idma_mask(channel->num),
569 IPU_CHA_BUF1_RDY(channel->num));
575 val = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num));
576 val &= ~idma_mask(channel->num);
577 ipu_cm_write(ipu, val, IPU_CHA_DB_MODE_SEL(channel->num));
587 * a channel's priority. Refer to Table 36-8 Calculated priority value.
588 * The sub-module that is the sink or source for the channel must enable
591 void ipu_idmac_enable_watermark(struct ipuv3_channel *channel, bool enable)
593 struct ipu_soc *ipu = channel->ipu;
599 val = ipu_idmac_read(ipu, IDMAC_WM_EN(channel->num));
601 val |= 1 << (channel->num % 32);
603 val &= ~(1 << (channel->num % 32));
604 ipu_idmac_write(ipu, val, IDMAC_WM_EN(channel->num));
730 * Links a source channel to a sink channel in the FSU.
1057 int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel,
1060 return ipu_map_irq(ipu, irq_type + channel->num);