Lines Matching defs:mode
251 * struct zynqmp_dp_mode - Configured mode of DisplayPort
254 * @pclock: pixel clock frequency of current mode
294 * @mode: current mode between IP core and sink device
317 struct zynqmp_dp_mode mode;
543 * @pclock: pixel clock for requested display mode
547 * clock @pclock. The @pclock is stored in the mode to be used in other
587 dp->mode.bw_code = bw_code;
588 dp->mode.lane_cnt = lane_cnt;
589 dp->mode.pclock = pclock;
590 return dp->mode.bw_code;
611 for (i = 0; i < dp->mode.lane_cnt; i++) {
628 for (i = 0; i < dp->mode.lane_cnt; i++)
648 dp->mode.lane_cnt);
652 for (i = 0; i < dp->mode.lane_cnt; i++) {
680 u8 lane_cnt = dp->mode.lane_cnt;
746 u8 lane_cnt = dp->mode.lane_cnt;
795 u8 bw_code = dp->mode.bw_code;
796 u8 lane_cnt = dp->mode.lane_cnt;
887 struct zynqmp_dp_mode *mode = &dp->mode;
888 u8 bw = mode->bw_code;
900 ret = zynqmp_dp_mode_configure(dp, mode->pclock, bw);
1183 * @mode: requested display mode
1190 const struct drm_display_mode *mode)
1198 vid_kbytes = mode->clock * (dp->config.bpp / 8);
1199 bw = drm_dp_bw_code_to_link_rate(dp->mode.bw_code);
1200 avg_bytes_per_tu = vid_kbytes * tu / (dp->mode.lane_cnt * bw / 1000);
1220 * @mode: requested display mode
1222 * Configure the main stream based on the requested mode @mode. Calculation is
1226 const struct drm_display_mode *mode)
1228 u8 lane_cnt = dp->mode.lane_cnt;
1232 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_HTOTAL, mode->htotal);
1233 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_VTOTAL, mode->vtotal);
1235 (!!(mode->flags & DRM_MODE_FLAG_PVSYNC) <<
1237 (!!(mode->flags & DRM_MODE_FLAG_PHSYNC) <<
1240 mode->hsync_end - mode->hsync_start);
1242 mode->vsync_end - mode->vsync_start);
1243 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_HRES, mode->hdisplay);
1244 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_VRES, mode->vdisplay);
1246 mode->htotal - mode->hsync_start);
1248 mode->vtotal - mode->vsync_start);
1250 /* In synchronous mode, set the dividers */
1252 reg = drm_dp_bw_code_to_link_rate(dp->mode.bw_code);
1254 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_M_VID, mode->clock);
1270 wpl = (mode->hdisplay * dp->config.bpp + 15) / 16;
1368 const struct drm_display_mode *mode)
1373 if (mode->clock > ZYNQMP_MAX_FREQ) {
1374 dev_dbg(dp->dev, "filtered mode %s for high pixel rate\n",
1375 mode->name);
1376 drm_mode_debug_printmodeline(mode);
1383 if (mode->clock > rate) {
1384 dev_dbg(dp->dev, "filtered mode %s for high pixel rate\n",
1385 mode->name);
1386 drm_mode_debug_printmodeline(mode);
1400 const struct drm_display_mode *mode;
1412 * Retrieve the CRTC mode and adjusted mode. This requires a little
1421 mode = &crtc_state->mode;
1429 if (mode->clock > rate) {
1430 dev_err(dp->dev, "mode %s has too high pixel rate\n",
1431 mode->name);
1432 drm_mode_debug_printmodeline(mode);
1435 /* Configure the mode */
1498 struct drm_display_mode *mode = &crtc_state->mode;
1500 int diff = mode->htotal - mode->hsync_end;
1655 !drm_dp_clock_recovery_ok(&status[2], dp->mode.lane_cnt) ||
1656 !drm_dp_channel_eq_ok(&status[2], dp->mode.lane_cnt)) {