Lines Matching defs:config
241 * struct zynqmp_dp_link_config - Common link config between source and sink
285 * @config: IP core configuration from DTS
307 struct zynqmp_dp_config config;
533 * Return: max pixel clock (KHz) supported by current link config.
560 u8 bpp = dp->config.bpp;
1089 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_MISC0, dp->config.misc0);
1090 zynqmp_dp_write(dp, ZYNQMP_DP_MAIN_STREAM_MISC1, dp->config.misc1);
1109 struct zynqmp_dp_config *config = &dp->config;
1112 config->misc0 &= ~ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_MASK;
1113 config->misc1 &= ~ZYNQMP_DP_MAIN_STREAM_MISC1_Y_ONLY_EN;
1117 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_RGB;
1122 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_YCRCB_444;
1127 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_COMP_FORMAT_YCRCB_422;
1132 config->misc1 |= ZYNQMP_DP_MAIN_STREAM_MISC1_Y_ONLY_EN;
1148 config->misc0 &= ~ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_MASK;
1152 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_6;
1155 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_8;
1158 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_10;
1161 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_12;
1164 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_16;
1169 config->misc0 |= ZYNQMP_DP_MAIN_STREAM_MISC0_BPC_8;
1175 config->bpp = bpc * num_colors;
1198 vid_kbytes = mode->clock * (dp->config.bpp / 8);
1251 if (dp->config.misc0 & ZYNQMP_DP_MAIN_STREAM_MISC0_SYNC_LOCK) {
1270 wpl = (mode->hdisplay * dp->config.bpp + 15) / 16;
1382 dp->link_config.max_lanes, dp->config.bpp);
1428 dp->link_config.max_lanes, dp->config.bpp);
1736 dp->config.misc0 &= ~ZYNQMP_DP_MAIN_STREAM_MISC0_SYNC_LOCK;