Lines Matching defs:clock
87 * 0x80000000 seems to be equivalent to the pixel clock
88 * (which itself is the VEC clock divided by 8).
90 * Reference values (with the default pixel clock of 13.5 MHz):
145 * Db center frequency for SECAM; the clock for this is the same as for
203 struct clk *clock;
528 clk_disable_unprepare(vec->clock);
571 * We need to set the clock rate each time we enable the encoder
573 * clock, and both drivers are requesting different rates.
577 ret = clk_set_rate(vec->clock, 108000000);
579 DRM_ERROR("Failed to set clock rate: %d\n", ret);
583 ret = clk_prepare_enable(vec->clock);
585 DRM_ERROR("Failed to turn on core clock: %d\n", ret);
776 vec->clock = devm_clk_get(dev, NULL);
777 if (IS_ERR(vec->clock)) {
778 ret = PTR_ERR(vec->clock);
780 DRM_ERROR("Failed to get clock: %d\n", ret);