Lines Matching refs:reg
291 u32 reg;
311 reg = HVS_READ(SCALER_DISPECTRL);
312 ret = FIELD_GET(SCALER_DISPECTRL_DSP2_MUX_MASK, reg);
319 reg = HVS_READ(SCALER_DISPCTRL);
320 ret = FIELD_GET(SCALER_DISPCTRL_DSP3_MUX_MASK, reg);
327 reg = HVS_READ(SCALER_DISPEOLN);
328 ret = FIELD_GET(SCALER_DISPEOLN_DSP4_MUX_MASK, reg);
335 reg = HVS_READ(SCALER_DISPDITHER);
336 ret = FIELD_GET(SCALER_DISPDITHER_DSP5_MUX_MASK, reg);
832 u32 reg, top;
898 reg = HVS_READ(SCALER_DISPECTRL);
899 reg &= ~SCALER_DISPECTRL_DSP2_MUX_MASK;
901 reg | VC4_SET_FIELD(0, SCALER_DISPECTRL_DSP2_MUX));
903 reg = HVS_READ(SCALER_DISPCTRL);
904 reg &= ~SCALER_DISPCTRL_DSP3_MUX_MASK;
906 reg | VC4_SET_FIELD(3, SCALER_DISPCTRL_DSP3_MUX));
908 reg = HVS_READ(SCALER_DISPEOLN);
909 reg &= ~SCALER_DISPEOLN_DSP4_MUX_MASK;
911 reg | VC4_SET_FIELD(3, SCALER_DISPEOLN_DSP4_MUX));
913 reg = HVS_READ(SCALER_DISPDITHER);
914 reg &= ~SCALER_DISPDITHER_DSP5_MUX_MASK;
916 reg | VC4_SET_FIELD(3, SCALER_DISPDITHER_DSP5_MUX));
981 reg = 0;
983 reg |= (top - 1) << 16;
984 HVS_WRITE(SCALER_DISPBASE2, reg);
985 reg = top;
987 reg |= (top - 1) << 16;
988 HVS_WRITE(SCALER_DISPBASE1, reg);
989 reg = top;
991 reg |= (top - 1) << 16;
992 HVS_WRITE(SCALER_DISPBASE0, reg);
1005 reg = 0;
1007 reg |= top << 16;
1008 HVS_WRITE(SCALER_DISPBASE2, reg);
1010 reg = top;
1012 reg |= top << 16;
1013 HVS_WRITE(SCALER_DISPBASE1, reg);
1015 reg = top;
1017 reg |= top << 16;
1018 HVS_WRITE(SCALER_DISPBASE0, reg);