Lines Matching defs:mode
128 vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode,
147 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode,
151 unsigned long long clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc, fmt);
159 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
168 drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_FULL;
519 const struct drm_display_mode *mode;
521 list_for_each_entry(mode, &connector->probed_modes, head) {
522 if (vc4_hdmi_mode_needs_scrambling(mode, 8, VC4_HDMI_OUTPUT_RGB)) {
904 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
911 connector, mode);
918 connector, mode,
1003 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1012 if (!vc4_hdmi_mode_needs_scrambling(mode,
1160 const struct drm_display_mode *mode)
1397 const struct drm_display_mode *mode)
1463 const struct drm_display_mode *mode)
1466 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1467 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1468 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
1469 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
1470 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
1472 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
1474 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
1476 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
1480 VC4_SET_FIELD(mode->crtc_vtotal -
1481 mode->crtc_vsync_end,
1495 VC4_SET_FIELD(mode->hdisplay * pixel_rep,
1499 VC4_SET_FIELD((mode->htotal -
1500 mode->hsync_end) * pixel_rep,
1502 VC4_SET_FIELD((mode->hsync_end -
1503 mode->hsync_start) * pixel_rep,
1505 VC4_SET_FIELD((mode->hsync_start -
1506 mode->hdisplay) * pixel_rep,
1527 const struct drm_display_mode *mode)
1532 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1533 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1534 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
1535 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
1536 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
1538 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
1540 VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
1541 u32 vertb = (VC4_SET_FIELD(mode->htotal >> (2 - pixel_rep),
1543 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
1547 VC4_SET_FIELD(mode->crtc_vtotal -
1548 mode->crtc_vsync_end,
1563 VC4_SET_FIELD(mode->hdisplay * pixel_rep,
1565 VC4_SET_FIELD((mode->hsync_start -
1566 mode->hdisplay) * pixel_rep,
1570 VC4_SET_FIELD((mode->htotal -
1571 mode->hsync_end) * pixel_rep,
1573 VC4_SET_FIELD((mode->hsync_end -
1574 mode->hsync_start) * pixel_rep,
1686 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1776 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode);
1801 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1813 vc4_hdmi->variant->csc_setup(vc4_hdmi, conn_state, mode);
1830 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1832 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1833 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1926 const struct drm_display_mode *mode,
1930 u8 vic = drm_match_cea_mode(mode);
2009 const struct drm_display_mode *mode,
2024 mode->hdisplay > 3840 && mode->vdisplay >= 2160 &&
2025 drm_mode_vrefresh(mode) >= 50)
2035 vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode,
2039 unsigned long long clock = mode->clock * 1000ULL;
2041 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
2056 const struct drm_display_mode *mode,
2061 clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc, fmt);
2062 if (vc4_hdmi_encoder_clock_valid(vc4_hdmi, mode, clock) != MODE_OK)
2073 const struct drm_display_mode *mode,
2084 if (vc4_hdmi_sink_supports_format_bpc(vc4_hdmi, info, mode, format, bpc)) {
2088 mode, bpc, format);
2098 if (vc4_hdmi_sink_supports_format_bpc(vc4_hdmi, info, mode, format, bpc)) {
2102 mode, bpc, format);
2117 const struct drm_display_mode *mode)
2129 mode, bpc);
2137 mode->hdisplay, mode->vdisplay, drm_mode_vrefresh(mode),
2162 struct drm_display_mode *mode = &crtc_state->adjusted_mode;
2163 unsigned long long tmds_char_rate = mode->clock * 1000;
2168 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
2175 if ((mode->hsync_start - mode->hdisplay) & 1)
2176 mode->hsync_start--;
2177 if ((mode->hsync_end - mode->hsync_start) & 1)
2178 mode->hsync_end--;
2182 if ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
2183 (mode->hsync_end % 2) || (mode->htotal % 2))
2197 mode->clock = 238560;
2198 tmds_char_rate = mode->clock * 1000;
2201 ret = vc4_hdmi_encoder_compute_config(vc4_hdmi, vc4_state, mode);
2215 const struct drm_display_mode *mode)
2220 !(mode->flags & DRM_MODE_FLAG_DBLCLK) &&
2221 ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
2222 (mode->hsync_end % 2) || (mode->htotal % 2)))
2225 return vc4_hdmi_encoder_clock_valid(vc4_hdmi, mode, mode->clock * 1000);
2325 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
2333 tmp = (u64)(mode->clock * 1000) * n;
2364 * If the encoder is currently in DVI mode, treat the codec DAI