Lines Matching defs:clock
13 * the unit operates off of the HSM clock from CPRMAN. It also
14 * internally uses the PLLH_PIX clock for the PHY.
151 unsigned long long clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc, fmt);
153 return clock > HDMI_14_MAX_TMDS_CLK;
284 * Set the clock divider: the hsm_clock rate and this divider
285 * setting will give a 40 kHz CEC clock.
400 * TMDS clock/data transmission should be suspended when
401 * changing the TMDS clock rate in the sink. So let's
523 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz.");
1705 * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must
1706 * be faster than pixel clock, infinitesimally faster, tested in
1709 * states HSM's clock has to be at least 108% of the pixel clock.
1714 * both clocks. Which, for RPi0-3 implies a maximum pixel clock of
1717 * Additionally, the AXI clock needs to be at least 25% of
1718 * pixel clock, but HSM ends up being the limiting factor.
1725 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
1731 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret);
1737 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
1753 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret);
1759 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret);
2010 unsigned long long clock)
2016 if (clock > vc4_hdmi->variant->max_pixel_clock)
2019 if (!vc4->hvs->vc5_hdmi_enable_hdmi_20 && clock > HDMI_14_MAX_TMDS_CLK)
2028 if (info->max_tmds_clock && clock > (info->max_tmds_clock * 1000))
2039 unsigned long long clock = mode->clock * 1000ULL;
2042 clock = clock * 2;
2047 clock = clock * bpc;
2048 do_div(clock, 8);
2050 return clock;
2059 unsigned long long clock;
2061 clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc, fmt);
2062 if (vc4_hdmi_encoder_clock_valid(vc4_hdmi, mode, clock) != MODE_OK)
2065 vc4_state->tmds_char_rate = clock;
2136 "Mode %ux%u @ %uHz: Found configuration: bpc: %u, fmt: %s, clock: %llu\n",
2163 unsigned long long tmds_char_rate = mode->clock * 1000;
2197 mode->clock = 238560;
2198 tmds_char_rate = mode->clock * 1000;
2225 return vc4_hdmi_encoder_clock_valid(vc4_hdmi, mode, mode->clock * 1000);
2333 tmp = (u64)(mode->clock * 1000) * n;
3054 /* clock period in microseconds */
3417 DRM_ERROR("Failed to get pixel clock\n");
3423 DRM_ERROR("Failed to get HDMI state machine clock\n");
3507 DRM_ERROR("Failed to get HDMI state machine clock\n");
3513 DRM_ERROR("Failed to get pixel bvb clock\n");
3519 DRM_ERROR("Failed to get audio clock\n");
3525 DRM_ERROR("Failed to get CEC clock\n");
3593 * plugged in, the firmware won't have initialized the HSM clock