Lines Matching defs:port
540 unsigned int port;
659 DSI_READ(dsi->variant->port ? DSI1_##offset : DSI0_##offset)
661 DSI_WRITE(dsi->variant->port ? DSI1_##offset : DSI0_##offset, val)
662 #define DSI_PORT_BIT(bit) (dsi->variant->port ? DSI1_##bit : DSI0_##bit)
896 DRM_ERROR("Failed to runtime PM enable on DSI%d\n", dsi->variant->port);
942 if (dsi->variant->port == 0) {
1091 (dsi->variant->port == 0 ?
1117 if (dsi->variant->port == 0)
1254 if (dsi->variant->port == 0) {
1436 .port = 1,
1443 .port = 0,
1450 .port = 1,
1471 DRM_ERROR("DSI%d: %s error\n", dsi->variant->port, type);
1476 * Initial handler for port 1 where we need the reg_dma workaround.
1493 * Normal IRQ handler for port 0, or the threaded IRQ handler for port
1521 if (stat & ((dsi->variant->port ? DSI1_INT_TXPKT1_DONE :
1571 "dsi%u_%s", dsi->variant->port, phy_clocks[i].name);
1662 dsi->encoder.type = dsi->variant->port ?