Lines Matching refs:arcpgu
61 static inline void arc_pgu_write(struct arcpgu_drm_private *arcpgu,
64 iowrite32(value, arcpgu->regs + reg);
67 static inline u32 arc_pgu_read(struct arcpgu_drm_private *arcpgu,
70 return ioread32(arcpgu->regs + reg);
116 static void arc_pgu_set_pxl_fmt(struct arcpgu_drm_private *arcpgu)
118 const struct drm_framebuffer *fb = arcpgu->pipe.plane.state->fb;
132 reg_ctrl = arc_pgu_read(arcpgu, ARCPGU_REG_CTRL);
137 arc_pgu_write(arcpgu, ARCPGU_REG_CTRL, reg_ctrl);
143 struct arcpgu_drm_private *arcpgu = pipe_to_arcpgu_priv(pipe);
147 rate = clk_round_rate(arcpgu->clk, clk_rate);
154 static void arc_pgu_mode_set(struct arcpgu_drm_private *arcpgu)
156 struct drm_display_mode *m = &arcpgu->pipe.crtc.state->adjusted_mode;
159 arc_pgu_write(arcpgu, ARCPGU_REG_FMT,
162 arc_pgu_write(arcpgu, ARCPGU_REG_HSYNC,
166 arc_pgu_write(arcpgu, ARCPGU_REG_VSYNC,
170 arc_pgu_write(arcpgu, ARCPGU_REG_ACTIVE,
174 val = arc_pgu_read(arcpgu, ARCPGU_REG_CTRL);
186 arc_pgu_write(arcpgu, ARCPGU_REG_CTRL, val);
187 arc_pgu_write(arcpgu, ARCPGU_REG_STRIDE, 0);
188 arc_pgu_write(arcpgu, ARCPGU_REG_START_SET, 1);
190 arc_pgu_set_pxl_fmt(arcpgu);
192 clk_set_rate(arcpgu->clk, m->crtc_clock * 1000);
199 struct arcpgu_drm_private *arcpgu = pipe_to_arcpgu_priv(pipe);
201 arc_pgu_mode_set(arcpgu);
203 clk_prepare_enable(arcpgu->clk);
204 arc_pgu_write(arcpgu, ARCPGU_REG_CTRL,
205 arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) |
211 struct arcpgu_drm_private *arcpgu = pipe_to_arcpgu_priv(pipe);
213 clk_disable_unprepare(arcpgu->clk);
214 arc_pgu_write(arcpgu, ARCPGU_REG_CTRL,
215 arc_pgu_read(arcpgu, ARCPGU_REG_CTRL) &
222 struct arcpgu_drm_private *arcpgu;
228 arcpgu = pipe_to_arcpgu_priv(pipe);
230 arc_pgu_write(arcpgu, ARCPGU_REG_BUF0_ADDR, gem->dma_addr);
248 static int arcpgu_load(struct arcpgu_drm_private *arcpgu)
250 struct platform_device *pdev = to_platform_device(arcpgu->drm.dev);
253 struct drm_device *drm = &arcpgu->drm;
257 arcpgu->clk = devm_clk_get(drm->dev, "pxlclk");
258 if (IS_ERR(arcpgu->clk))
259 return PTR_ERR(arcpgu->clk);
272 arcpgu->regs = devm_ioremap_resource(&pdev->dev, res);
273 if (IS_ERR(arcpgu->regs))
274 return PTR_ERR(arcpgu->regs);
277 arc_pgu_read(arcpgu, ARCPGU_REG_ID));
296 connector = &arcpgu->sim_conn;
303 ret = drm_simple_display_pipe_init(drm, &arcpgu->pipe, &arc_pgu_pipe_funcs,
318 ret = drm_simple_display_pipe_attach_bridge(&arcpgu->pipe, bridge);
343 struct arcpgu_drm_private *arcpgu = dev_to_arcpgu(drm);
344 unsigned long clkrate = clk_get_rate(arcpgu->clk);
345 unsigned long mode_clock = arcpgu->pipe.crtc.mode.crtc_clock * 1000;
366 .name = "arcpgu",
381 struct arcpgu_drm_private *arcpgu;
384 arcpgu = devm_drm_dev_alloc(&pdev->dev, &arcpgu_drm_driver,
386 if (IS_ERR(arcpgu))
387 return PTR_ERR(arcpgu);
389 ret = arcpgu_load(arcpgu);
393 ret = drm_dev_register(&arcpgu->drm, 0);
397 drm_fbdev_dma_setup(&arcpgu->drm, 16);
402 arcpgu_unload(&arcpgu->drm);
418 {.compatible = "snps,arcpgu"},
428 .name = "arcpgu",