Lines Matching refs:dispc
360 static void dispc_write(struct dispc_device *dispc, u16 reg, u32 val)
362 iowrite32(val, dispc->base_common + reg);
365 static u32 dispc_read(struct dispc_device *dispc, u16 reg)
367 return ioread32(dispc->base_common + reg);
371 void dispc_vid_write(struct dispc_device *dispc, u32 hw_plane, u16 reg, u32 val)
373 void __iomem *base = dispc->base_vid[hw_plane];
378 static u32 dispc_vid_read(struct dispc_device *dispc, u32 hw_plane, u16 reg)
380 void __iomem *base = dispc->base_vid[hw_plane];
385 static void dispc_ovr_write(struct dispc_device *dispc, u32 hw_videoport,
388 void __iomem *base = dispc->base_ovr[hw_videoport];
393 static u32 dispc_ovr_read(struct dispc_device *dispc, u32 hw_videoport, u16 reg)
395 void __iomem *base = dispc->base_ovr[hw_videoport];
400 static void dispc_vp_write(struct dispc_device *dispc, u32 hw_videoport,
403 void __iomem *base = dispc->base_vp[hw_videoport];
408 static u32 dispc_vp_read(struct dispc_device *dispc, u32 hw_videoport, u16 reg)
410 void __iomem *base = dispc->base_vp[hw_videoport];
440 static u32 REG_GET(struct dispc_device *dispc, u32 idx, u32 start, u32 end)
442 return FLD_GET(dispc_read(dispc, idx), start, end);
445 static void REG_FLD_MOD(struct dispc_device *dispc, u32 idx, u32 val,
448 dispc_write(dispc, idx, FLD_MOD(dispc_read(dispc, idx), val,
452 static u32 VID_REG_GET(struct dispc_device *dispc, u32 hw_plane, u32 idx,
455 return FLD_GET(dispc_vid_read(dispc, hw_plane, idx), start, end);
458 static void VID_REG_FLD_MOD(struct dispc_device *dispc, u32 hw_plane, u32 idx,
461 dispc_vid_write(dispc, hw_plane, idx,
462 FLD_MOD(dispc_vid_read(dispc, hw_plane, idx),
466 static u32 VP_REG_GET(struct dispc_device *dispc, u32 vp, u32 idx,
469 return FLD_GET(dispc_vp_read(dispc, vp, idx), start, end);
472 static void VP_REG_FLD_MOD(struct dispc_device *dispc, u32 vp, u32 idx, u32 val,
475 dispc_vp_write(dispc, vp, idx, FLD_MOD(dispc_vp_read(dispc, vp, idx),
480 static u32 OVR_REG_GET(struct dispc_device *dispc, u32 ovr, u32 idx,
483 return FLD_GET(dispc_ovr_read(dispc, ovr, idx), start, end);
486 static void OVR_REG_FLD_MOD(struct dispc_device *dispc, u32 ovr, u32 idx,
489 dispc_ovr_write(dispc, ovr, idx,
490 FLD_MOD(dispc_ovr_read(dispc, ovr, idx),
546 static dispc_irq_t dispc_k2g_vp_read_irqstatus(struct dispc_device *dispc,
549 u32 stat = dispc_vp_read(dispc, hw_videoport, DISPC_VP_K2G_IRQSTATUS);
554 static void dispc_k2g_vp_write_irqstatus(struct dispc_device *dispc,
559 dispc_vp_write(dispc, hw_videoport, DISPC_VP_K2G_IRQSTATUS, stat);
562 static dispc_irq_t dispc_k2g_vid_read_irqstatus(struct dispc_device *dispc,
565 u32 stat = dispc_vid_read(dispc, hw_plane, DISPC_VID_K2G_IRQSTATUS);
570 static void dispc_k2g_vid_write_irqstatus(struct dispc_device *dispc,
575 dispc_vid_write(dispc, hw_plane, DISPC_VID_K2G_IRQSTATUS, stat);
578 static dispc_irq_t dispc_k2g_vp_read_irqenable(struct dispc_device *dispc,
581 u32 stat = dispc_vp_read(dispc, hw_videoport, DISPC_VP_K2G_IRQENABLE);
586 static void dispc_k2g_vp_set_irqenable(struct dispc_device *dispc,
591 dispc_vp_write(dispc, hw_videoport, DISPC_VP_K2G_IRQENABLE, stat);
594 static dispc_irq_t dispc_k2g_vid_read_irqenable(struct dispc_device *dispc,
597 u32 stat = dispc_vid_read(dispc, hw_plane, DISPC_VID_K2G_IRQENABLE);
602 static void dispc_k2g_vid_set_irqenable(struct dispc_device *dispc,
607 dispc_vid_write(dispc, hw_plane, DISPC_VID_K2G_IRQENABLE, stat);
610 static void dispc_k2g_clear_irqstatus(struct dispc_device *dispc,
613 dispc_k2g_vp_write_irqstatus(dispc, 0, mask);
614 dispc_k2g_vid_write_irqstatus(dispc, 0, mask);
618 dispc_irq_t dispc_k2g_read_and_clear_irqstatus(struct dispc_device *dispc)
623 dispc_write(dispc, DISPC_IRQSTATUS,
624 dispc_read(dispc, DISPC_IRQSTATUS));
626 stat |= dispc_k2g_vp_read_irqstatus(dispc, 0);
627 stat |= dispc_k2g_vid_read_irqstatus(dispc, 0);
629 dispc_k2g_clear_irqstatus(dispc, stat);
634 static dispc_irq_t dispc_k2g_read_irqenable(struct dispc_device *dispc)
638 stat |= dispc_k2g_vp_read_irqenable(dispc, 0);
639 stat |= dispc_k2g_vid_read_irqenable(dispc, 0);
645 void dispc_k2g_set_irqenable(struct dispc_device *dispc, dispc_irq_t mask)
647 dispc_irq_t old_mask = dispc_k2g_read_irqenable(dispc);
650 dispc_k2g_clear_irqstatus(dispc, (mask ^ old_mask) & mask);
652 dispc_k2g_vp_set_irqenable(dispc, 0, mask);
653 dispc_k2g_vid_set_irqenable(dispc, 0, mask);
655 dispc_write(dispc, DISPC_IRQENABLE_SET, (1 << 0) | (1 << 7));
658 dispc_k2g_read_irqenable(dispc);
661 static dispc_irq_t dispc_k3_vp_read_irqstatus(struct dispc_device *dispc,
664 u32 stat = dispc_read(dispc, DISPC_VP_IRQSTATUS(hw_videoport));
669 static void dispc_k3_vp_write_irqstatus(struct dispc_device *dispc,
674 dispc_write(dispc, DISPC_VP_IRQSTATUS(hw_videoport), stat);
677 static dispc_irq_t dispc_k3_vid_read_irqstatus(struct dispc_device *dispc,
680 u32 stat = dispc_read(dispc, DISPC_VID_IRQSTATUS(hw_plane));
685 static void dispc_k3_vid_write_irqstatus(struct dispc_device *dispc,
690 dispc_write(dispc, DISPC_VID_IRQSTATUS(hw_plane), stat);
693 static dispc_irq_t dispc_k3_vp_read_irqenable(struct dispc_device *dispc,
696 u32 stat = dispc_read(dispc, DISPC_VP_IRQENABLE(hw_videoport));
701 static void dispc_k3_vp_set_irqenable(struct dispc_device *dispc,
706 dispc_write(dispc, DISPC_VP_IRQENABLE(hw_videoport), stat);
709 static dispc_irq_t dispc_k3_vid_read_irqenable(struct dispc_device *dispc,
712 u32 stat = dispc_read(dispc, DISPC_VID_IRQENABLE(hw_plane));
717 static void dispc_k3_vid_set_irqenable(struct dispc_device *dispc,
722 dispc_write(dispc, DISPC_VID_IRQENABLE(hw_plane), stat);
726 void dispc_k3_clear_irqstatus(struct dispc_device *dispc, dispc_irq_t clearmask)
731 for (i = 0; i < dispc->feat->num_vps; ++i) {
733 dispc_k3_vp_write_irqstatus(dispc, i, clearmask);
737 for (i = 0; i < dispc->feat->num_planes; ++i) {
739 dispc_k3_vid_write_irqstatus(dispc, i, clearmask);
743 if (dispc->feat->subrev == DISPC_K2G)
746 dispc_write(dispc, DISPC_IRQSTATUS, top_clear);
749 dispc_read(dispc, DISPC_IRQSTATUS);
753 dispc_irq_t dispc_k3_read_and_clear_irqstatus(struct dispc_device *dispc)
758 for (i = 0; i < dispc->feat->num_vps; ++i)
759 status |= dispc_k3_vp_read_irqstatus(dispc, i);
761 for (i = 0; i < dispc->feat->num_planes; ++i)
762 status |= dispc_k3_vid_read_irqstatus(dispc, i);
764 dispc_k3_clear_irqstatus(dispc, status);
769 static dispc_irq_t dispc_k3_read_irqenable(struct dispc_device *dispc)
774 for (i = 0; i < dispc->feat->num_vps; ++i)
775 enable |= dispc_k3_vp_read_irqenable(dispc, i);
777 for (i = 0; i < dispc->feat->num_planes; ++i)
778 enable |= dispc_k3_vid_read_irqenable(dispc, i);
783 static void dispc_k3_set_irqenable(struct dispc_device *dispc,
790 old_mask = dispc_k3_read_irqenable(dispc);
793 dispc_k3_clear_irqstatus(dispc, (old_mask ^ mask) & mask);
795 for (i = 0; i < dispc->feat->num_vps; ++i) {
796 dispc_k3_vp_set_irqenable(dispc, i, mask);
803 for (i = 0; i < dispc->feat->num_planes; ++i) {
804 dispc_k3_vid_set_irqenable(dispc, i, mask);
812 dispc_write(dispc, DISPC_IRQENABLE_SET, main_enable);
815 dispc_write(dispc, DISPC_IRQENABLE_CLR, main_disable);
818 dispc_read(dispc, DISPC_IRQENABLE_SET);
821 dispc_irq_t dispc_read_and_clear_irqstatus(struct dispc_device *dispc)
823 switch (dispc->feat->subrev) {
825 return dispc_k2g_read_and_clear_irqstatus(dispc);
829 return dispc_k3_read_and_clear_irqstatus(dispc);
836 void dispc_set_irqenable(struct dispc_device *dispc, dispc_irq_t mask)
838 switch (dispc->feat->subrev) {
840 dispc_k2g_set_irqenable(dispc, mask);
845 dispc_k3_set_irqenable(dispc, mask);
875 struct dispc_bus_format *dispc_vp_find_bus_fmt(struct dispc_device *dispc,
889 int dispc_vp_bus_check(struct dispc_device *dispc, u32 hw_videoport,
895 fmt = dispc_vp_find_bus_fmt(dispc, hw_videoport, tstate->bus_format,
898 dev_dbg(dispc->dev, "%s: Unsupported bus format: %u\n",
903 if (dispc->feat->vp_bus_type[hw_videoport] != DISPC_VP_OLDI &&
905 dev_dbg(dispc->dev, "%s: %s is not OLDI-port\n",
906 __func__, dispc->feat->vp_name[hw_videoport]);
913 static void dispc_oldi_tx_power(struct dispc_device *dispc, bool power)
917 if (WARN_ON(!dispc->oldi_io_ctrl))
920 regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT0_IO_CTRL,
922 regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT1_IO_CTRL,
924 regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT2_IO_CTRL,
926 regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT3_IO_CTRL,
928 regmap_update_bits(dispc->oldi_io_ctrl, OLDI_CLK_IO_CTRL,
932 static void dispc_set_num_datalines(struct dispc_device *dispc,
955 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, v, 10, 8);
958 static void dispc_enable_oldi(struct dispc_device *dispc, u32 hw_videoport,
973 dev_warn(dispc->dev, "%s: %d port width not supported\n",
984 dispc_vp_write(dispc, hw_videoport, DISPC_VP_DSS_OLDI_CFG, oldi_cfg);
986 while (!(oldi_reset_bit & dispc_read(dispc, DSS_SYSSTATUS)) &&
990 if (!(oldi_reset_bit & dispc_read(dispc, DSS_SYSSTATUS)))
991 dev_warn(dispc->dev, "%s: timeout waiting OLDI reset done\n",
995 void dispc_vp_prepare(struct dispc_device *dispc, u32 hw_videoport,
1001 fmt = dispc_vp_find_bus_fmt(dispc, hw_videoport, tstate->bus_format,
1007 if (dispc->feat->vp_bus_type[hw_videoport] == DISPC_VP_OLDI) {
1008 dispc_oldi_tx_power(dispc, true);
1010 dispc_enable_oldi(dispc, hw_videoport, fmt);
1014 void dispc_vp_enable(struct dispc_device *dispc, u32 hw_videoport,
1023 fmt = dispc_vp_find_bus_fmt(dispc, hw_videoport, tstate->bus_format,
1029 dispc_set_num_datalines(dispc, hw_videoport, fmt->data_width);
1039 dispc_vp_write(dispc, hw_videoport, DISPC_VP_TIMING_H,
1044 dispc_vp_write(dispc, hw_videoport, DISPC_VP_TIMING_V,
1066 if (dispc->feat->vp_bus_type[hw_videoport] == DISPC_VP_OLDI)
1069 dispc_vp_write(dispc, hw_videoport, DISPC_VP_POL_FREQ,
1078 dispc_vp_write(dispc, hw_videoport, DISPC_VP_SIZE_SCREEN,
1082 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, 0, 0);
1085 void dispc_vp_disable(struct dispc_device *dispc, u32 hw_videoport)
1087 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 0, 0, 0);
1090 void dispc_vp_unprepare(struct dispc_device *dispc, u32 hw_videoport)
1092 if (dispc->feat->vp_bus_type[hw_videoport] == DISPC_VP_OLDI) {
1093 dispc_vp_write(dispc, hw_videoport, DISPC_VP_DSS_OLDI_CFG, 0);
1095 dispc_oldi_tx_power(dispc, false);
1099 bool dispc_vp_go_busy(struct dispc_device *dispc, u32 hw_videoport)
1101 return VP_REG_GET(dispc, hw_videoport, DISPC_VP_CONTROL, 5, 5);
1104 void dispc_vp_go(struct dispc_device *dispc, u32 hw_videoport)
1106 WARN_ON(VP_REG_GET(dispc, hw_videoport, DISPC_VP_CONTROL, 5, 5));
1107 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, 5, 5);
1150 static void dispc_vp_set_default_color(struct dispc_device *dispc,
1157 dispc_ovr_write(dispc, hw_videoport,
1159 dispc_ovr_write(dispc, hw_videoport,
1163 enum drm_mode_status dispc_vp_mode_valid(struct dispc_device *dispc,
1171 bus_type = dispc->feat->vp_bus_type[hw_videoport];
1173 max_pclk = dispc->feat->max_pclk_khz[bus_type];
1178 if (mode->clock < dispc->feat->min_pclk_khz)
1222 if (dispc->memory_bandwidth_limit) {
1230 if (dispc->memory_bandwidth_limit < bandwidth)
1237 int dispc_vp_enable_clk(struct dispc_device *dispc, u32 hw_videoport)
1239 int ret = clk_prepare_enable(dispc->vp_clk[hw_videoport]);
1242 dev_err(dispc->dev, "%s: enabling clk failed: %d\n", __func__,
1248 void dispc_vp_disable_clk(struct dispc_device *dispc, u32 hw_videoport)
1250 clk_disable_unprepare(dispc->vp_clk[hw_videoport]);
1265 int dispc_vp_set_clk_rate(struct dispc_device *dispc, u32 hw_videoport,
1271 r = clk_set_rate(dispc->vp_clk[hw_videoport], rate);
1273 dev_err(dispc->dev, "vp%d: failed to set clk rate to %lu\n",
1278 new_rate = clk_get_rate(dispc->vp_clk[hw_videoport]);
1281 dev_warn(dispc->dev,
1285 dev_dbg(dispc->dev, "vp%d: new rate %lu Hz (requested %lu Hz)\n",
1286 hw_videoport, clk_get_rate(dispc->vp_clk[hw_videoport]), rate);
1292 static void dispc_k2g_ovr_set_plane(struct dispc_device *dispc,
1297 dispc_vid_write(dispc, hw_plane, DISPC_VID_K2G_POSITION,
1301 static void dispc_am65x_ovr_set_plane(struct dispc_device *dispc,
1305 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer),
1307 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer),
1309 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer),
1313 static void dispc_j721e_ovr_set_plane(struct dispc_device *dispc,
1317 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer),
1319 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES2(layer),
1321 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES2(layer),
1325 void dispc_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane,
1328 switch (dispc->feat->subrev) {
1330 dispc_k2g_ovr_set_plane(dispc, hw_plane, hw_videoport,
1335 dispc_am65x_ovr_set_plane(dispc, hw_plane, hw_videoport,
1339 dispc_j721e_ovr_set_plane(dispc, hw_plane, hw_videoport,
1348 void dispc_ovr_enable_layer(struct dispc_device *dispc,
1351 if (dispc->feat->subrev == DISPC_K2G)
1354 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer),
1437 static void dispc_k2g_vid_write_csc(struct dispc_device *dispc, u32 hw_plane,
1452 dev_warn(dispc->dev, "%s: No post offset support for %s\n",
1456 dispc_vid_write(dispc, hw_plane, dispc_vid_csc_coef_reg[i],
1460 static void dispc_k3_vid_write_csc(struct dispc_device *dispc, u32 hw_plane,
1475 dispc_vid_write(dispc, hw_plane, dispc_vid_csc_coef_reg[i],
1557 static void dispc_vid_csc_setup(struct dispc_device *dispc, u32 hw_plane,
1564 dev_err(dispc->dev, "%s: CSC (%u,%u) not found\n",
1569 if (dispc->feat->subrev == DISPC_K2G)
1570 dispc_k2g_vid_write_csc(dispc, hw_plane, coef);
1572 dispc_k3_vid_write_csc(dispc, hw_plane, coef);
1575 static void dispc_vid_csc_enable(struct dispc_device *dispc, u32 hw_plane,
1578 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable, 9, 9);
1595 static void dispc_vid_write_fir_coefs(struct dispc_device *dispc,
1619 dev_err(dispc->dev, "%s: No coefficients given.\n", __func__);
1627 dispc_vid_write(dispc, hw_plane, reg, c0);
1639 dispc_vid_write(dispc, hw_plane, reg, c12);
1664 static int dispc_vid_calc_scaling(struct dispc_device *dispc,
1669 const struct dispc_features_scaling *f = &dispc->feat->scaling;
1718 dev_dbg(dispc->dev,
1731 dev_dbg(dispc->dev,
1748 dev_dbg(dispc->dev,
1769 dev_dbg(dispc->dev,
1787 dev_dbg(dispc->dev,
1803 sp->xcoef_uv = tidss_get_scale_coefs(dispc->dev,
1811 sp->ycoef_uv = tidss_get_scale_coefs(dispc->dev,
1818 sp->xcoef = tidss_get_scale_coefs(dispc->dev, sp->fir_xinc,
1822 sp->ycoef = tidss_get_scale_coefs(dispc->dev, sp->fir_yinc,
1828 static void dispc_vid_set_scaling(struct dispc_device *dispc,
1834 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES,
1838 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES,
1846 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES,
1851 dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRH2,
1853 dispc_vid_write_fir_coefs(dispc, hw_plane,
1858 dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRV2,
1860 dispc_vid_write_fir_coefs(dispc, hw_plane,
1867 dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRH, sp->fir_xinc);
1868 dispc_vid_write_fir_coefs(dispc, hw_plane,
1874 dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRV, sp->fir_yinc);
1875 dispc_vid_write_fir_coefs(dispc, hw_plane,
1928 static void dispc_plane_set_pixel_format(struct dispc_device *dispc,
1935 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES,
1945 const u32 *dispc_plane_formats(struct dispc_device *dispc, unsigned int *len)
1947 WARN_ON(!dispc->fourccs);
1949 *len = dispc->num_fourccs;
1951 return dispc->fourccs;
1967 int dispc_plane_check(struct dispc_device *dispc, u32 hw_plane,
1971 bool lite = dispc->feat->vid_lite[hw_plane];
1981 dev_dbg(dispc->dev,
1991 dev_dbg(dispc->dev,
1998 ret = dispc_vid_calc_scaling(dispc, state, &scaling, false);
2038 void dispc_plane_setup(struct dispc_device *dispc, u32 hw_plane,
2042 bool lite = dispc->feat->vid_lite[hw_plane];
2049 dispc_vid_calc_scaling(dispc, state, &scale, lite);
2051 dispc_plane_set_pixel_format(dispc, hw_plane, fourcc);
2053 dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_0, dma_addr & 0xffffffff);
2054 dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_EXT_0, (u64)dma_addr >> 32);
2055 dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_1, dma_addr & 0xffffffff);
2056 dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_EXT_1, (u64)dma_addr >> 32);
2058 dispc_vid_write(dispc, hw_plane, DISPC_VID_PICTURE_SIZE,
2063 dispc_vid_write(dispc, hw_plane, DISPC_VID_PIXEL_INC,
2066 dispc_vid_write(dispc, hw_plane, DISPC_VID_PIXEL_INC,
2069 dispc_vid_write(dispc, hw_plane, DISPC_VID_ROW_INC,
2079 dispc_vid_write(dispc, hw_plane,
2081 dispc_vid_write(dispc, hw_plane,
2083 dispc_vid_write(dispc, hw_plane,
2085 dispc_vid_write(dispc, hw_plane,
2088 dispc_vid_write(dispc, hw_plane, DISPC_VID_ROW_INC_UV,
2095 dispc_vid_write(dispc, hw_plane, DISPC_VID_SIZE,
2099 dispc_vid_set_scaling(dispc, hw_plane, &scale, fourcc);
2104 dispc_vid_csc_setup(dispc, hw_plane, state);
2105 dispc_vid_csc_enable(dispc, hw_plane, true);
2107 dispc_vid_csc_enable(dispc, hw_plane, false);
2110 dispc_vid_write(dispc, hw_plane, DISPC_VID_GLOBAL_ALPHA,
2114 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 1,
2117 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 0,
2121 void dispc_plane_enable(struct dispc_device *dispc, u32 hw_plane, bool enable)
2123 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable, 0, 0);
2126 static u32 dispc_vid_get_fifo_size(struct dispc_device *dispc, u32 hw_plane)
2128 return VID_REG_GET(dispc, hw_plane, DISPC_VID_BUF_SIZE_STATUS, 15, 0);
2131 static void dispc_vid_set_mflag_threshold(struct dispc_device *dispc,
2134 dispc_vid_write(dispc, hw_plane, DISPC_VID_MFLAG_THRESHOLD,
2138 static void dispc_vid_set_buf_threshold(struct dispc_device *dispc,
2141 dispc_vid_write(dispc, hw_plane, DISPC_VID_BUF_THRESHOLD,
2145 static void dispc_k2g_plane_init(struct dispc_device *dispc)
2149 dev_dbg(dispc->dev, "%s()\n", __func__);
2152 REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 2, 1, 0);
2154 REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, 6, 6);
2156 for (hw_plane = 0; hw_plane < dispc->feat->num_planes; hw_plane++) {
2157 u32 size = dispc_vid_get_fifo_size(dispc, hw_plane);
2170 dev_dbg(dispc->dev,
2172 dispc->feat->vid_name[hw_plane],
2178 dispc_vid_set_buf_threshold(dispc, hw_plane,
2180 dispc_vid_set_mflag_threshold(dispc, hw_plane,
2183 dispc_vid_write(dispc, hw_plane, DISPC_VID_PRELOAD, preload);
2190 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 1,
2195 static void dispc_k3_plane_init(struct dispc_device *dispc)
2201 dev_dbg(dispc->dev, "%s()\n", __func__);
2203 REG_FLD_MOD(dispc, DSS_CBA_CFG, cba_lo_pri, 2, 0);
2204 REG_FLD_MOD(dispc, DSS_CBA_CFG, cba_hi_pri, 5, 3);
2207 REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 2, 1, 0);
2209 REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, 6, 6);
2211 for (hw_plane = 0; hw_plane < dispc->feat->num_planes; hw_plane++) {
2212 u32 size = dispc_vid_get_fifo_size(dispc, hw_plane);
2225 dev_dbg(dispc->dev,
2227 dispc->feat->vid_name[hw_plane],
2233 dispc_vid_set_buf_threshold(dispc, hw_plane,
2235 dispc_vid_set_mflag_threshold(dispc, hw_plane,
2238 dispc_vid_write(dispc, hw_plane, DISPC_VID_PRELOAD, preload);
2241 VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 0,
2246 static void dispc_plane_init(struct dispc_device *dispc)
2248 switch (dispc->feat->subrev) {
2250 dispc_k2g_plane_init(dispc);
2255 dispc_k3_plane_init(dispc);
2262 static void dispc_vp_init(struct dispc_device *dispc)
2266 dev_dbg(dispc->dev, "%s()\n", __func__);
2269 for (i = 0; i < dispc->feat->num_vps; i++)
2270 VP_REG_FLD_MOD(dispc, i, DISPC_VP_CONFIG, 1, 2, 2);
2273 static void dispc_initial_config(struct dispc_device *dispc)
2275 dispc_plane_init(dispc);
2276 dispc_vp_init(dispc);
2279 if (dispc->feat->subrev == DISPC_J721E) {
2280 dispc_write(dispc, DISPC_CONNECTIONS,
2287 static void dispc_k2g_vp_write_gamma_table(struct dispc_device *dispc,
2290 u32 *table = dispc->vp_data[hw_videoport].gamma_table;
2291 u32 hwlen = dispc->feat->vp_feat.color.gamma_size;
2294 dev_dbg(dispc->dev, "%s: hw_videoport %d\n", __func__, hw_videoport);
2296 if (WARN_ON(dispc->feat->vp_feat.color.gamma_type != TIDSS_GAMMA_8BIT))
2304 dispc_vp_write(dispc, hw_videoport, DISPC_VP_K2G_GAMMA_TABLE,
2309 static void dispc_am65x_vp_write_gamma_table(struct dispc_device *dispc,
2312 u32 *table = dispc->vp_data[hw_videoport].gamma_table;
2313 u32 hwlen = dispc->feat->vp_feat.color.gamma_size;
2316 dev_dbg(dispc->dev, "%s: hw_videoport %d\n", __func__, hw_videoport);
2318 if (WARN_ON(dispc->feat->vp_feat.color.gamma_type != TIDSS_GAMMA_8BIT))
2326 dispc_vp_write(dispc, hw_videoport, DISPC_VP_GAMMA_TABLE, v);
2330 static void dispc_j721e_vp_write_gamma_table(struct dispc_device *dispc,
2333 u32 *table = dispc->vp_data[hw_videoport].gamma_table;
2334 u32 hwlen = dispc->feat->vp_feat.color.gamma_size;
2337 dev_dbg(dispc->dev, "%s: hw_videoport %d\n", __func__, hw_videoport);
2339 if (WARN_ON(dispc->feat->vp_feat.color.gamma_type != TIDSS_GAMMA_10BIT))
2348 dispc_vp_write(dispc, hw_videoport, DISPC_VP_GAMMA_TABLE, v);
2352 static void dispc_vp_write_gamma_table(struct dispc_device *dispc,
2355 switch (dispc->feat->subrev) {
2357 dispc_k2g_vp_write_gamma_table(dispc, hw_videoport);
2361 dispc_am65x_vp_write_gamma_table(dispc, hw_videoport);
2364 dispc_j721e_vp_write_gamma_table(dispc, hw_videoport);
2377 static void dispc_vp_set_gamma(struct dispc_device *dispc,
2382 u32 *table = dispc->vp_data[hw_videoport].gamma_table;
2383 u32 hwlen = dispc->feat->vp_feat.color.gamma_size;
2387 dev_dbg(dispc->dev, "%s: hw_videoport %d, lut len %u, hw len %u\n",
2390 if (dispc->feat->vp_feat.color.gamma_type == TIDSS_GAMMA_10BIT)
2424 dispc_vp_write_gamma_table(dispc, hw_videoport);
2471 static void dispc_k2g_vp_write_csc(struct dispc_device *dispc, u32 hw_videoport,
2484 dispc_vp_write(dispc, hw_videoport, dispc_vp_cpr_coef_reg[i],
2488 static void dispc_k2g_vp_set_ctm(struct dispc_device *dispc, u32 hw_videoport,
2497 dispc_k2g_vp_write_csc(dispc, hw_videoport, &cpr);
2501 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONFIG,
2536 static void dispc_k3_vp_write_csc(struct dispc_device *dispc, u32 hw_videoport,
2550 dispc_vp_write(dispc, hw_videoport, dispc_vp_csc_coef_reg[i],
2554 static void dispc_k3_vp_set_ctm(struct dispc_device *dispc, u32 hw_videoport,
2563 dispc_k3_vp_write_csc(dispc, hw_videoport, &csc);
2567 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONFIG,
2571 static void dispc_vp_set_color_mgmt(struct dispc_device *dispc,
2588 dispc_vp_set_gamma(dispc, hw_videoport, lut, length);
2593 if (dispc->feat->subrev == DISPC_K2G)
2594 dispc_k2g_vp_set_ctm(dispc, hw_videoport, ctm);
2596 dispc_k3_vp_set_ctm(dispc, hw_videoport, ctm);
2599 void dispc_vp_setup(struct dispc_device *dispc, u32 hw_videoport,
2602 dispc_vp_set_default_color(dispc, hw_videoport, 0);
2603 dispc_vp_set_color_mgmt(dispc, hw_videoport, state, newmodeset);
2606 int dispc_runtime_suspend(struct dispc_device *dispc)
2608 dev_dbg(dispc->dev, "suspend\n");
2610 dispc->is_enabled = false;
2612 clk_disable_unprepare(dispc->fclk);
2617 int dispc_runtime_resume(struct dispc_device *dispc)
2619 dev_dbg(dispc->dev, "resume\n");
2621 clk_prepare_enable(dispc->fclk);
2623 if (REG_GET(dispc, DSS_SYSSTATUS, 0, 0) == 0)
2624 dev_warn(dispc->dev, "DSS FUNC RESET not done!\n");
2626 dev_dbg(dispc->dev, "OMAP DSS7 rev 0x%x\n",
2627 dispc_read(dispc, DSS_REVISION));
2629 dev_dbg(dispc->dev, "VP RESETDONE %d,%d,%d\n",
2630 REG_GET(dispc, DSS_SYSSTATUS, 1, 1),
2631 REG_GET(dispc, DSS_SYSSTATUS, 2, 2),
2632 REG_GET(dispc, DSS_SYSSTATUS, 3, 3));
2634 if (dispc->feat->subrev == DISPC_AM625 ||
2635 dispc->feat->subrev == DISPC_AM65X)
2636 dev_dbg(dispc->dev, "OLDI RESETDONE %d,%d,%d\n",
2637 REG_GET(dispc, DSS_SYSSTATUS, 5, 5),
2638 REG_GET(dispc, DSS_SYSSTATUS, 6, 6),
2639 REG_GET(dispc, DSS_SYSSTATUS, 7, 7));
2641 dev_dbg(dispc->dev, "DISPC IDLE %d\n",
2642 REG_GET(dispc, DSS_SYSSTATUS, 9, 9));
2644 dispc_initial_config(dispc);
2646 dispc->is_enabled = true;
2648 tidss_irq_resume(dispc->tidss);
2657 tidss->dispc = NULL;
2677 struct dispc_device *dispc)
2679 dispc->oldi_io_ctrl =
2682 if (PTR_ERR(dispc->oldi_io_ctrl) == -ENODEV) {
2683 dispc->oldi_io_ctrl = NULL;
2684 } else if (IS_ERR(dispc->oldi_io_ctrl)) {
2686 __func__, PTR_ERR(dispc->oldi_io_ctrl));
2687 return PTR_ERR(dispc->oldi_io_ctrl);
2692 static void dispc_init_errata(struct dispc_device *dispc)
2700 dispc->errata.i2000 = true;
2701 dev_info(dispc->dev, "WA for erratum i2000: YUV formats disabled\n");
2705 static int dispc_softreset(struct dispc_device *dispc)
2711 if (dispc->feat->subrev == DISPC_K2G)
2715 REG_FLD_MOD(dispc, DSS_SYSCONFIG, 1, 1, 1);
2717 ret = readl_poll_timeout(dispc->base_common + DSS_SYSSTATUS,
2720 dev_err(dispc->dev, "failed to reset dispc\n");
2727 static int dispc_init_hw(struct dispc_device *dispc)
2729 struct device *dev = dispc->dev;
2738 ret = clk_prepare_enable(dispc->fclk);
2744 ret = dispc_softreset(dispc);
2748 clk_disable_unprepare(dispc->fclk);
2758 clk_disable_unprepare(dispc->fclk);
2774 struct dispc_device *dispc;
2791 dispc = devm_kzalloc(dev, sizeof(*dispc), GFP_KERNEL);
2792 if (!dispc)
2795 dispc->tidss = tidss;
2796 dispc->dev = dev;
2797 dispc->feat = feat;
2799 dispc_init_errata(dispc);
2801 dispc->fourccs = devm_kcalloc(dev, ARRAY_SIZE(dispc_color_formats),
2802 sizeof(*dispc->fourccs), GFP_KERNEL);
2803 if (!dispc->fourccs)
2808 if (dispc->errata.i2000 &&
2812 dispc->fourccs[num_fourccs++] = dispc_color_formats[i].fourcc;
2815 dispc->num_fourccs = num_fourccs;
2817 dispc_common_regmap = dispc->feat->common_regs;
2819 r = dispc_iomap_resource(pdev, dispc->feat->common,
2820 &dispc->base_common);
2824 for (i = 0; i < dispc->feat->num_planes; i++) {
2825 r = dispc_iomap_resource(pdev, dispc->feat->vid_name[i],
2826 &dispc->base_vid[i]);
2831 for (i = 0; i < dispc->feat->num_vps; i++) {
2832 u32 gamma_size = dispc->feat->vp_feat.color.gamma_size;
2836 r = dispc_iomap_resource(pdev, dispc->feat->ovr_name[i],
2837 &dispc->base_ovr[i]);
2841 r = dispc_iomap_resource(pdev, dispc->feat->vp_name[i],
2842 &dispc->base_vp[i]);
2846 clk = devm_clk_get(dev, dispc->feat->vpclk_name[i]);
2849 dispc->feat->vpclk_name[i], PTR_ERR(clk));
2852 dispc->vp_clk[i] = clk;
2859 dispc->vp_data[i].gamma_table = gamma_table;
2863 r = dispc_init_am65x_oldi_io_ctrl(dev, dispc);
2868 dispc->fclk = devm_clk_get(dev, "fck");
2869 if (IS_ERR(dispc->fclk)) {
2871 __func__, PTR_ERR(dispc->fclk));
2872 return PTR_ERR(dispc->fclk);
2874 dev_dbg(dev, "DSS fclk %lu Hz\n", clk_get_rate(dispc->fclk));
2876 of_property_read_u32(dispc->dev->of_node, "max-memory-bandwidth",
2877 &dispc->memory_bandwidth_limit);
2879 r = dispc_init_hw(dispc);
2883 tidss->dispc = dispc;