Lines Matching refs:pclk
450 unsigned long pclk;
1157 const u64 pclk = (u64)mode->clock * 1000;
1163 if (!link_rate || !link->lanes || !pclk || !config->bits_per_pixel)
1166 input = pclk * config->bits_per_pixel;
1174 params.num_clocks = div_u64(link_rate * mode->hdisplay, pclk);
1225 config->hblank_symbols = div_u64(num, pclk);
1234 config->vblank_symbols = div_u64(num, pclk);
1807 unsigned long pclk = crtc_state->mode.clock * 1000;
1818 if (pclk >= 340000000) {
1820 state->pclk = pclk / 2;
1823 state->pclk = pclk;
1827 pclk, 0);
2252 unsigned long rate, pclk;
2259 pclk = mode->clock * 1000;
2425 DRM_DEBUG_KMS("setting clock to %lu Hz, mode: %lu Hz\n", rate, pclk);