Lines Matching defs:value
486 u32 value = readl(sor->regs + (offset << 2));
488 trace_sor_readl(sor->dev, offset, value);
490 return value;
493 static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value,
496 trace_sor_writel(sor->dev, offset, value);
497 writel(value, sor->regs + (offset << 2));
544 u32 value;
546 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
547 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
551 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK;
555 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
559 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
569 u32 value;
571 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
573 switch (value & SOR_CLK_CNTRL_DP_CLK_SEL_MASK) {
647 u32 value;
653 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
656 value &= ~(SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) |
659 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) |
663 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]);
665 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]);
668 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]);
670 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]);
672 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
675 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
677 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
682 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
683 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
689 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0)
698 u32 value;
701 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
702 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
704 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
707 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP |
709 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
714 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
715 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
721 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0)
729 u32 value;
732 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
735 value &= ~(SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) |
738 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) |
742 value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]);
744 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]);
747 value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]);
749 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]);
751 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
755 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
756 value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 |
758 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
763 u32 mask = 0x08, adj = 0, value;
766 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
767 value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
768 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
770 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
771 value |= SOR_PLL1_TMDS_TERM;
772 tegra_sor_writel(sor, value, sor->soc->regs->pll1);
777 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
778 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
779 value |= SOR_PLL1_TMDS_TERMADJ(adj);
780 tegra_sor_writel(sor, value, sor->soc->regs->pll1);
784 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
785 if (value & SOR_PLL1_TERM_COMPOUT)
791 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
792 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
793 value |= SOR_PLL1_TMDS_TERMADJ(adj);
794 tegra_sor_writel(sor, value, sor->soc->regs->pll1);
797 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
798 value |= SOR_DP_PADCTL_PAD_CAL_PD;
799 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
807 u32 pattern = 0, tx_pu = 0, value;
810 for (value = 0, i = 0; i < link->lanes; i++) {
825 value = SOR_DP_TPG_SCRAMBLER_GALIOS |
830 value = SOR_DP_TPG_SCRAMBLER_NONE |
835 value = SOR_DP_TPG_SCRAMBLER_NONE |
840 value = SOR_DP_TPG_SCRAMBLER_NONE |
849 value |= SOR_DP_TPG_CHANNEL_CODING;
851 pattern = pattern << 8 | value;
862 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
863 value &= ~SOR_DP_PADCTL_TX_PU_MASK;
864 value |= SOR_DP_PADCTL_TX_PU_ENABLE;
865 value |= SOR_DP_PADCTL_TX_PU(tx_pu);
866 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
877 u32 value;
884 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
885 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
886 value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate);
887 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
889 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
890 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
891 value |= SOR_DP_LINKCTL_LANE_COUNT(lanes);
894 value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
896 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
901 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
902 value &= ~SOR_PLL1_LOADADJ_MASK;
906 value |= SOR_PLL1_LOADADJ(0x3);
910 value |= SOR_PLL1_LOADADJ(0x4);
914 value |= SOR_PLL1_LOADADJ(0x6);
918 tegra_sor_writel(sor, value, sor->soc->regs->pll1);
921 value = tegra_sor_readl(sor, SOR_DP_SPARE0);
924 value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
926 value |= SOR_DP_SPARE_PANEL_INTERNAL;
928 tegra_sor_writel(sor, value, SOR_DP_SPARE0);
970 u32 value;
972 value = tegra_sor_readl(sor, SOR_PWM_DIV);
973 value &= ~SOR_PWM_DIV_MASK;
974 value |= 0x400; /* period */
975 tegra_sor_writel(sor, value, SOR_PWM_DIV);
977 value = tegra_sor_readl(sor, SOR_PWM_CTL);
978 value &= ~SOR_PWM_CTL_DUTY_CYCLE_MASK;
979 value |= 0x400; /* duty cycle */
980 value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */
981 value |= SOR_PWM_CTL_TRIGGER;
982 tegra_sor_writel(sor, value, SOR_PWM_CTL);
987 value = tegra_sor_readl(sor, SOR_PWM_CTL);
988 if ((value & SOR_PWM_CTL_TRIGGER) == 0)
999 unsigned long value, timeout;
1002 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1003 value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE;
1004 value |= SOR_SUPER_STATE_MODE_NORMAL;
1005 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1009 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1010 value |= SOR_SUPER_STATE_ATTACHED;
1011 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1017 value = tegra_sor_readl(sor, SOR_TEST);
1018 if ((value & SOR_TEST_ATTACHED) != 0)
1029 unsigned long value, timeout;
1035 value = tegra_sor_readl(sor, SOR_TEST);
1036 value &= SOR_TEST_HEAD_MODE_MASK;
1038 if (value == SOR_TEST_HEAD_MODE_AWAKE)
1049 u32 value;
1051 value = tegra_sor_readl(sor, SOR_PWR);
1052 value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU;
1053 tegra_sor_writel(sor, value, SOR_PWR);
1058 value = tegra_sor_readl(sor, SOR_PWR);
1059 if ((value & SOR_PWR_TRIGGER) == 0)
1246 u32 value;
1248 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
1249 value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK;
1250 value |= SOR_DP_LINKCTL_TU_SIZE(config->tu_size);
1251 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1253 value = tegra_sor_readl(sor, SOR_DP_CONFIG0);
1254 value &= ~SOR_DP_CONFIG_WATERMARK_MASK;
1255 value |= SOR_DP_CONFIG_WATERMARK(config->watermark);
1257 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK;
1258 value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config->active_count);
1260 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK;
1261 value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config->active_frac);
1264 value |= SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
1266 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
1268 value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE;
1269 value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE;
1270 tegra_sor_writel(sor, value, SOR_DP_CONFIG0);
1272 value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS);
1273 value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK;
1274 value |= config->hblank_symbols & 0xffff;
1275 tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS);
1277 value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS);
1278 value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK;
1279 value |= config->vblank_symbols & 0xffff;
1280 tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS);
1289 u32 value;
1291 value = tegra_sor_readl(sor, SOR_STATE1);
1292 value &= ~SOR_STATE_ASY_PIXELDEPTH_MASK;
1293 value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
1294 value &= ~SOR_STATE_ASY_OWNER_MASK;
1296 value |= SOR_STATE_ASY_CRC_MODE_COMPLETE |
1300 value &= ~SOR_STATE_ASY_HSYNCPOL;
1303 value |= SOR_STATE_ASY_HSYNCPOL;
1306 value &= ~SOR_STATE_ASY_VSYNCPOL;
1309 value |= SOR_STATE_ASY_VSYNCPOL;
1313 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_48_444;
1317 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_36_444;
1321 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_30_444;
1325 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
1329 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444;
1333 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
1337 tegra_sor_writel(sor, value, SOR_STATE1);
1344 value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff);
1345 tegra_sor_writel(sor, value, sor->soc->regs->head_state1 + dc->pipe);
1351 value = ((vse & 0x7fff) << 16) | (hse & 0x7fff);
1352 tegra_sor_writel(sor, value, sor->soc->regs->head_state2 + dc->pipe);
1358 value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff);
1359 tegra_sor_writel(sor, value, sor->soc->regs->head_state3 + dc->pipe);
1365 value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff);
1366 tegra_sor_writel(sor, value, sor->soc->regs->head_state4 + dc->pipe);
1374 unsigned long value, timeout;
1377 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1378 value &= ~SOR_SUPER_STATE_MODE_NORMAL;
1379 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1385 value = tegra_sor_readl(sor, SOR_PWR);
1386 if (value & SOR_PWR_MODE_SAFE)
1390 if ((value & SOR_PWR_MODE_SAFE) == 0)
1394 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1395 value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK;
1396 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1400 value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1401 value &= ~SOR_SUPER_STATE_ATTACHED;
1402 tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1408 value = tegra_sor_readl(sor, SOR_TEST);
1409 if ((value & SOR_TEST_ATTACHED) == 0)
1415 if ((value & SOR_TEST_ATTACHED) != 0)
1423 unsigned long value, timeout;
1426 value = tegra_sor_readl(sor, SOR_PWR);
1427 value &= ~SOR_PWR_NORMAL_STATE_PU;
1428 value |= SOR_PWR_TRIGGER;
1429 tegra_sor_writel(sor, value, SOR_PWR);
1434 value = tegra_sor_readl(sor, SOR_PWR);
1435 if ((value & SOR_PWR_TRIGGER) == 0)
1441 if ((value & SOR_PWR_TRIGGER) != 0)
1451 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1452 value |= SOR_PLL2_PORT_POWERDOWN;
1453 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1457 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
1458 value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR;
1459 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
1461 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1462 value |= SOR_PLL2_SEQ_PLLCAPPD;
1463 value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
1464 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1473 u32 value;
1478 value = tegra_sor_readl(sor, SOR_CRCA);
1479 if (value & SOR_CRCA_VALID)
1495 u32 value;
1504 value = tegra_sor_readl(sor, SOR_STATE1);
1505 value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
1506 tegra_sor_writel(sor, value, SOR_STATE1);
1508 value = tegra_sor_readl(sor, SOR_CRC_CNTRL);
1509 value |= SOR_CRC_CNTRL_ENABLE;
1510 tegra_sor_writel(sor, value, SOR_CRC_CNTRL);
1512 value = tegra_sor_readl(sor, SOR_TEST);
1513 value &= ~SOR_TEST_CRC_POST_SERIALIZE;
1514 tegra_sor_writel(sor, value, SOR_TEST);
1521 value = tegra_sor_readl(sor, SOR_CRCB);
1523 seq_printf(s, "%08x\n", value);
1850 u32 value = 0;
1854 value = (value << 8) | ptr[i - 1];
1856 return value;
1865 u32 value;
1886 value = INFOFRAME_HEADER_TYPE(ptr[0]) |
1889 tegra_sor_writel(sor, value, offset);
1900 value = tegra_sor_hdmi_subpack(&ptr[i], num);
1901 tegra_sor_writel(sor, value, offset++);
1905 value = tegra_sor_hdmi_subpack(&ptr[i + 4], num);
1906 tegra_sor_writel(sor, value, offset++);
1916 u32 value;
1920 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL);
1921 value &= ~INFOFRAME_CTRL_SINGLE;
1922 value &= ~INFOFRAME_CTRL_OTHER;
1923 value &= ~INFOFRAME_CTRL_ENABLE;
1924 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL);
1942 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL);
1943 value |= INFOFRAME_CTRL_CHECKSUM_ENABLE;
1944 value |= INFOFRAME_CTRL_ENABLE;
1945 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL);
1970 u32 value;
1977 value = SOR_INT_CODEC_SCRATCH1 | SOR_INT_CODEC_SCRATCH0;
1978 tegra_sor_writel(sor, value, SOR_INT_ENABLE);
1979 tegra_sor_writel(sor, value, SOR_INT_MASK);
1983 value = SOR_AUDIO_HDA_PRESENSE_ELDV | SOR_AUDIO_HDA_PRESENSE_PD;
1984 tegra_sor_writel(sor, value, SOR_AUDIO_HDA_PRESENSE);
1996 u32 value;
1998 value = tegra_sor_readl(sor, SOR_AUDIO_CNTRL);
2001 value &= ~SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_MASK);
2002 value |= SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_HDA);
2006 value &= ~SOR_AUDIO_CNTRL_INJECT_NULLSMPL;
2008 value |= SOR_AUDIO_CNTRL_INJECT_NULLSMPL;
2010 value |= SOR_AUDIO_CNTRL_AFIFO_FLUSH;
2012 tegra_sor_writel(sor, value, SOR_AUDIO_CNTRL);
2022 u32 value;
2041 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2042 value |= INFOFRAME_CTRL_CHECKSUM_ENABLE;
2043 value |= INFOFRAME_CTRL_ENABLE;
2044 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2051 u32 value;
2057 value = SOR_HDMI_SPARE_ACR_PRIORITY_HIGH |
2060 tegra_sor_writel(sor, value, SOR_HDMI_SPARE);
2063 value = SOR_HDMI_ACR_SUBPACK_LOW_SB1(0);
2064 tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_LOW);
2067 value = SOR_HDMI_ACR_SUBPACK_HIGH_ENABLE;
2068 tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_HIGH);
2071 value = SOR_HDMI_AUDIO_N_RESET | SOR_HDMI_AUDIO_N_LOOKUP;
2072 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N);
2074 value = (24000 * 4096) / (128 * sor->format.sample_rate / 1000);
2075 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0320);
2087 value = (24000 * 6144) / (128 * sor->format.sample_rate / 1000);
2088 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0480);
2091 value = (24000 * 12288) / (128 * sor->format.sample_rate / 1000);
2092 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0960);
2095 value = (24000 * 24576) / (128 * sor->format.sample_rate / 1000);
2096 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_1920);
2099 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_N);
2100 value &= ~SOR_HDMI_AUDIO_N_RESET;
2101 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N);
2108 u32 value;
2110 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2111 value &= ~INFOFRAME_CTRL_ENABLE;
2112 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2134 u32 value;
2136 value = tegra_sor_readl(sor, SOR_HDMI2_CTRL);
2137 value &= ~SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4;
2138 value &= ~SOR_HDMI2_CTRL_SCRAMBLE;
2139 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL);
2160 u32 value;
2162 value = tegra_sor_readl(sor, SOR_HDMI2_CTRL);
2163 value |= SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4;
2164 value |= SOR_HDMI2_CTRL_SCRAMBLE;
2165 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL);
2207 u32 value;
2221 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2224 value &= ~SOR1_TIMING_CYA;
2226 value &= ~SOR_ENABLE(sor->index);
2228 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2254 u32 value;
2282 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2283 value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
2284 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2288 value = tegra_sor_readl(sor, sor->soc->regs->pll3);
2289 value &= ~SOR_PLL3_PLL_VDD_MODE_3V3;
2290 tegra_sor_writel(sor, value, sor->soc->regs->pll3);
2292 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2293 value &= ~SOR_PLL0_VCOPD;
2294 value &= ~SOR_PLL0_PWR;
2295 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2297 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2298 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
2299 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2303 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2304 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
2305 value &= ~SOR_PLL2_PORT_POWERDOWN;
2306 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2310 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2311 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
2313 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2316 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
2317 if ((value & SOR_LANE_SEQ_CTL_STATE_BUSY) == 0)
2323 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
2325 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
2328 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
2329 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
2335 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
2336 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
2337 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
2341 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70;
2344 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40;
2347 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK;
2348 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
2353 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
2354 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
2355 value |= SOR_DP_LINKCTL_LANE_COUNT(4);
2356 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
2358 value = tegra_sor_readl(sor, SOR_DP_SPARE0);
2359 value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE;
2360 value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
2361 value &= ~SOR_DP_SPARE_SEQ_ENABLE;
2362 value &= ~SOR_DP_SPARE_MACRO_SOR_CLK;
2363 tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2365 value = SOR_SEQ_CTL_PU_PC(0) | SOR_SEQ_CTL_PU_PC_ALT(0) |
2367 tegra_sor_writel(sor, value, SOR_SEQ_CTL);
2369 value = SOR_SEQ_INST_DRIVE_PWM_OUT_LO | SOR_SEQ_INST_HALT |
2371 tegra_sor_writel(sor, value, SOR_SEQ_INST(0));
2372 tegra_sor_writel(sor, value, SOR_SEQ_INST(8));
2376 value = SOR_REFCLK_DIV_INT(div) | SOR_REFCLK_DIV_FRAC(div);
2377 tegra_sor_writel(sor, value, SOR_REFCLK);
2381 for (value = 0, i = 0; i < 5; i++)
2382 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->xbar_cfg[i]) |
2386 tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
2430 value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe);
2434 value |= SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED;
2436 tegra_sor_writel(sor, value, SOR_INPUT_CONTROL);
2441 value = SOR_HDMI_CTRL_ENABLE | SOR_HDMI_CTRL_MAX_AC_PACKET(max_ac) |
2443 tegra_sor_writel(sor, value, SOR_HDMI_CTRL);
2451 value = PULSE_LAST_END_A | PULSE_QUAL_VACTIVE |
2453 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
2455 value = PULSE_END(pulse_start + 8) | PULSE_START(pulse_start);
2456 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
2458 value = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0);
2459 value |= H_PULSE2_ENABLE;
2460 tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0);
2472 value = tegra_sor_readl(sor, SOR_STATE1);
2473 value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
2474 value |= SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A;
2475 tegra_sor_writel(sor, value, SOR_STATE1);
2478 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2479 value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
2480 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2490 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2491 value &= ~SOR_PLL0_ICHPMP_MASK;
2492 value &= ~SOR_PLL0_FILTER_MASK;
2493 value &= ~SOR_PLL0_VCOCAP_MASK;
2494 value |= SOR_PLL0_ICHPMP(settings->ichpmp);
2495 value |= SOR_PLL0_FILTER(settings->filter);
2496 value |= SOR_PLL0_VCOCAP(settings->vcocap);
2497 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2500 value = tegra_sor_readl(sor, sor->soc->regs->pll1);
2501 value &= ~SOR_PLL1_LOADADJ_MASK;
2502 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
2503 value |= SOR_PLL1_LOADADJ(settings->loadadj);
2504 value |= SOR_PLL1_TMDS_TERMADJ(settings->tmds_termadj);
2505 value |= SOR_PLL1_TMDS_TERM;
2506 tegra_sor_writel(sor, value, sor->soc->regs->pll1);
2508 value = tegra_sor_readl(sor, sor->soc->regs->pll3);
2509 value &= ~SOR_PLL3_BG_TEMP_COEF_MASK;
2510 value &= ~SOR_PLL3_BG_VREF_LEVEL_MASK;
2511 value &= ~SOR_PLL3_AVDD10_LEVEL_MASK;
2512 value &= ~SOR_PLL3_AVDD14_LEVEL_MASK;
2513 value |= SOR_PLL3_BG_TEMP_COEF(settings->bg_temp_coef);
2514 value |= SOR_PLL3_BG_VREF_LEVEL(settings->bg_vref_level);
2515 value |= SOR_PLL3_AVDD10_LEVEL(settings->avdd10_level);
2516 value |= SOR_PLL3_AVDD14_LEVEL(settings->avdd14_level);
2517 tegra_sor_writel(sor, value, sor->soc->regs->pll3);
2519 value = settings->drive_current[3] << 24 |
2523 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0);
2525 value = settings->preemphasis[3] << 24 |
2529 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0);
2531 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2532 value &= ~SOR_DP_PADCTL_TX_PU_MASK;
2533 value |= SOR_DP_PADCTL_TX_PU_ENABLE;
2534 value |= SOR_DP_PADCTL_TX_PU(settings->tx_pu_value);
2535 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2537 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl2);
2538 value &= ~SOR_DP_PADCTL_SPAREPLL_MASK;
2539 value |= SOR_DP_PADCTL_SPAREPLL(settings->sparepll);
2540 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl2);
2543 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2544 value |= SOR_DP_PADCTL_PAD_CAL_PD;
2545 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2549 value = VSYNC_H_POSITION(1);
2550 tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS);
2553 value = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
2554 value &= ~DITHER_CONTROL_MASK;
2555 value &= ~BASE_COLOR_SIZE_MASK;
2559 value |= BASE_COLOR_SIZE_666;
2563 value |= BASE_COLOR_SIZE_888;
2567 value |= BASE_COLOR_SIZE_101010;
2571 value |= BASE_COLOR_SIZE_121212;
2576 value |= BASE_COLOR_SIZE_888;
2580 tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL);
2583 value = tegra_sor_readl(sor, SOR_STATE1);
2584 value &= ~SOR_STATE_ASY_OWNER_MASK;
2585 value |= SOR_STATE_ASY_OWNER(1 + dc->pipe);
2586 tegra_sor_writel(sor, value, SOR_STATE1);
2593 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe);
2594 value &= ~SOR_HEAD_STATE_RANGECOMPRESS_MASK;
2595 value &= ~SOR_HEAD_STATE_DYNRANGE_MASK;
2596 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe);
2599 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe);
2600 value &= ~SOR_HEAD_STATE_COLORSPACE_MASK;
2601 value |= SOR_HEAD_STATE_COLORSPACE_RGB;
2602 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe);
2609 value = tegra_sor_readl(sor, SOR_DP_SPARE0);
2610 value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE;
2611 tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2618 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2621 value |= SOR1_TIMING_CYA;
2623 value |= SOR_ENABLE(sor->index);
2625 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2628 value = tegra_dc_readl(dc, DC_DISP_CORE_SOR_SET_CONTROL(sor->index));
2629 value &= ~PROTOCOL_MASK;
2630 value |= PROTOCOL_SINGLE_TMDS_A;
2631 tegra_dc_writel(dc, value, DC_DISP_CORE_SOR_SET_CONTROL(sor->index));
2655 u32 value;
2679 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2680 value &= ~SOR_ENABLE(sor->index);
2681 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2684 value = tegra_sor_readl(sor, SOR_STATE1);
2685 value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
2686 value &= ~SOR_STATE_ASY_SUBOWNER_MASK;
2687 value &= ~SOR_STATE_ASY_OWNER_MASK;
2688 tegra_sor_writel(sor, value, SOR_STATE1);
2724 u32 value;
2765 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2766 value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
2767 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2771 value = tegra_sor_readl(sor, sor->soc->regs->pll3);
2772 value |= SOR_PLL3_PLL_VDD_MODE_3V3;
2773 tegra_sor_writel(sor, value, sor->soc->regs->pll3);
2775 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2776 value &= ~(SOR_PLL0_VCOPD | SOR_PLL0_PWR);
2777 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2779 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2780 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
2781 value |= SOR_PLL2_SEQ_PLLCAPPD;
2782 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2786 value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2787 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
2788 value &= ~SOR_PLL2_PORT_POWERDOWN;
2789 tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2791 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
2792 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
2795 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
2797 value |= SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK;
2799 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
2803 value = tegra_sor_readl(sor, SOR_DP_SPARE0);
2806 value |= SOR_DP_SPARE_PANEL_INTERNAL;
2808 value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
2810 value |= SOR_DP_SPARE_SEQ_ENABLE;
2811 tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2816 value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2817 value &= ~SOR_PLL0_ICHPMP_MASK;
2818 value &= ~SOR_PLL0_VCOCAP_MASK;
2819 value |= SOR_PLL0_ICHPMP(0x1);
2820 value |= SOR_PLL0_VCOCAP(0x3);
2821 value |= SOR_PLL0_RESISTOR_EXT;
2822 tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2825 for (value = 0, i = 0; i < 5; i++)
2826 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) |
2830 tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
2864 value = tegra_sor_readl(sor, SOR_STATE1);
2865 value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
2866 value |= SOR_STATE_ASY_PROTOCOL_DP_A;
2867 tegra_sor_writel(sor, value, SOR_STATE1);
2870 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
2871 value |= SOR_DP_LINKCTL_ENABLE;
2872 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
2899 value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B |
2901 tegra_sor_writel(sor, value, SOR_CSTM);
2920 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2921 value |= SOR_ENABLE(sor->index);
2922 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
3642 u32 value;
3646 err = of_property_read_u32(np, "nvidia,interface", &value);
3650 sor->index = value;
3681 u32 value;
3683 value = tegra_sor_readl(sor, SOR_INT_STATUS);
3684 tegra_sor_writel(sor, value, SOR_INT_STATUS);
3686 if (value & SOR_INT_CODEC_SCRATCH0) {
3687 value = tegra_sor_readl(sor, SOR_AUDIO_HDA_CODEC_SCRATCH0);
3689 if (value & SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID) {
3692 format = value & SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK;