Lines Matching defs:link
424 struct drm_dp_link link;
622 struct drm_dp_link *link = &sor->link;
626 for (i = 0; i < link->num_rates; i++) {
627 switch (link->rates[i]) {
634 DRM_DEBUG_KMS("link rate %lu kHz not supported\n",
635 link->rates[i]);
636 link->rates[i] = 0;
641 drm_dp_link_update_rates(link);
802 static int tegra_sor_dp_link_apply_training(struct drm_dp_link *link)
804 struct tegra_sor *sor = container_of(link, struct tegra_sor, link);
810 for (value = 0, i = 0; i < link->lanes; i++) {
811 u8 vs = link->train.request.voltage_swing[i];
812 u8 pe = link->train.request.pre_emphasis[i];
813 u8 pc = link->train.request.post_cursor[i];
823 switch (link->train.pattern) {
848 if (link->caps.channel_coding)
857 if (link->caps.tps3_supported)
873 static int tegra_sor_dp_link_configure(struct drm_dp_link *link)
875 struct tegra_sor *sor = container_of(link, struct tegra_sor, link);
880 rate = drm_dp_link_rate_to_bw_code(link->rate);
881 lanes = link->lanes;
883 /* configure link speed and lane count */
893 if (link->caps.enhanced_framing)
923 if (link->edp == 0)
1069 /* number of link clocks per line */
1154 struct drm_dp_link *link)
1156 const u64 f = 100000, link_rate = link->rate * 1000;
1163 if (!link_rate || !link->lanes || !pclk || !config->bits_per_pixel)
1167 output = link_rate * 8 * link->lanes;
1210 (link->lanes * 8);
1227 if (link->caps.enhanced_framing)
1230 config->hblank_symbols -= 12 / link->lanes;
1235 config->vblank_symbols -= 36 / link->lanes + 4;
2340 DRM_DEBUG_KMS("setting 2.7 GHz link speed\n");
2343 DRM_DEBUG_KMS("setting 5.4 GHz link speed\n");
2662 * Do not attempt to power down a DP link if we're not connected since
2666 err = drm_dp_link_power_down(sor->aux, &sor->link);
2668 dev_err(sor->dev, "failed to power down link: %d\n",
2752 err = drm_dp_link_probe(sor->aux, &sor->link);
2754 dev_err(sor->dev, "failed to probe DP link: %d\n", err);
2758 err = drm_dp_link_choose(&sor->link, mode, info);
2760 dev_err(sor->dev, "failed to choose link: %d\n", err);
2876 err = drm_dp_link_train(&sor->link);
2878 dev_err(sor->dev, "link training failed: %d\n", err);
2880 dev_dbg(sor->dev, "link training succeeded\n");
2882 err = drm_dp_link_power_up(sor->aux, &sor->link);
2884 dev_err(sor->dev, "failed to power up DP link: %d\n", err);
2890 err = tegra_sor_compute_config(sor, mode, &config, &sor->link);
2898 /* CSTM (LVDS, link A/B, upper) */
3066 sor->link.ops = &tegra_sor_dp_link_ops;
3067 sor->link.aux = sor->aux;