Lines Matching refs:nvdec
36 struct nvdec {
55 static inline struct nvdec *to_nvdec(struct tegra_drm_client *client)
57 return container_of(client, struct nvdec, client);
60 static inline void nvdec_writel(struct nvdec *nvdec, u32 value,
63 writel(value, nvdec->regs + offset);
66 static int nvdec_boot_falcon(struct nvdec *nvdec)
71 if (nvdec->config->supports_sid && tegra_dev_iommu_get_stream_id(nvdec->dev, &stream_id)) {
75 nvdec_writel(nvdec, value, NVDEC_TFBIF_TRANSCFG);
77 nvdec_writel(nvdec, stream_id, VIC_THI_STREAMID0);
78 nvdec_writel(nvdec, stream_id, VIC_THI_STREAMID1);
81 err = falcon_boot(&nvdec->falcon);
85 err = falcon_wait_idle(&nvdec->falcon);
87 dev_err(nvdec->dev, "falcon boot timed out\n");
94 static int nvdec_wait_debuginfo(struct nvdec *nvdec, const char *phase)
99 err = readl_poll_timeout(nvdec->regs + NVDEC_FALCON_DEBUGINFO, val, val == 0x0, 10, 100000);
101 dev_err(nvdec->dev, "failed to boot %s, debuginfo=0x%x\n", phase, val);
108 static int nvdec_boot_riscv(struct nvdec *nvdec)
112 err = reset_control_acquire(nvdec->reset);
116 nvdec_writel(nvdec, 0xabcd1234, NVDEC_FALCON_DEBUGINFO);
118 err = tegra_drm_riscv_boot_bootrom(&nvdec->riscv, nvdec->carveout_base, 1,
119 &nvdec->riscv.bl_desc);
121 dev_err(nvdec->dev, "failed to execute bootloader\n");
125 err = nvdec_wait_debuginfo(nvdec, "bootloader");
129 err = reset_control_reset(nvdec->reset);
133 nvdec_writel(nvdec, 0xabcd1234, NVDEC_FALCON_DEBUGINFO);
135 err = tegra_drm_riscv_boot_bootrom(&nvdec->riscv, nvdec->carveout_base, 1,
136 &nvdec->riscv.os_desc);
138 dev_err(nvdec->dev, "failed to execute firmware\n");
142 err = nvdec_wait_debuginfo(nvdec, "firmware");
147 reset_control_release(nvdec->reset);
157 struct nvdec *nvdec = to_nvdec(drm);
162 dev_err(nvdec->dev, "failed to attach to domain: %d\n", err);
166 nvdec->channel = host1x_channel_request(client);
167 if (!nvdec->channel) {
193 host1x_channel_put(nvdec->channel);
205 struct nvdec *nvdec = to_nvdec(drm);
219 host1x_channel_put(nvdec->channel);
222 nvdec->channel = NULL;
225 dma_unmap_single(nvdec->dev, nvdec->falcon.firmware.phys,
226 nvdec->falcon.firmware.size, DMA_TO_DEVICE);
227 tegra_drm_free(tegra, nvdec->falcon.firmware.size,
228 nvdec->falcon.firmware.virt,
229 nvdec->falcon.firmware.iova);
231 dma_free_coherent(nvdec->dev, nvdec->falcon.firmware.size,
232 nvdec->falcon.firmware.virt,
233 nvdec->falcon.firmware.iova);
244 static int nvdec_load_falcon_firmware(struct nvdec *nvdec)
246 struct host1x_client *client = &nvdec->client.base;
247 struct tegra_drm *tegra = nvdec->client.drm;
253 if (nvdec->falcon.firmware.virt)
256 err = falcon_read_firmware(&nvdec->falcon, nvdec->config->firmware);
260 size = nvdec->falcon.firmware.size;
263 virt = dma_alloc_coherent(nvdec->dev, size, &iova, GFP_KERNEL);
265 err = dma_mapping_error(nvdec->dev, iova);
274 nvdec->falcon.firmware.virt = virt;
275 nvdec->falcon.firmware.iova = iova;
277 err = falcon_load_firmware(&nvdec->falcon);
289 phys = dma_map_single(nvdec->dev, virt, size, DMA_TO_DEVICE);
291 err = dma_mapping_error(nvdec->dev, phys);
295 nvdec->falcon.firmware.phys = phys;
302 dma_free_coherent(nvdec->dev, size, virt, iova);
311 struct nvdec *nvdec = dev_get_drvdata(dev);
314 err = clk_bulk_prepare_enable(nvdec->num_clks, nvdec->clks);
320 if (nvdec->config->has_riscv) {
321 err = nvdec_boot_riscv(nvdec);
325 err = nvdec_load_falcon_firmware(nvdec);
329 err = nvdec_boot_falcon(nvdec);
337 clk_bulk_disable_unprepare(nvdec->num_clks, nvdec->clks);
343 struct nvdec *nvdec = dev_get_drvdata(dev);
345 host1x_channel_stop(nvdec->channel);
347 clk_bulk_disable_unprepare(nvdec->num_clks, nvdec->clks);
355 struct nvdec *nvdec = to_nvdec(client);
357 context->channel = host1x_channel_get(nvdec->channel);
384 #define NVIDIA_TEGRA_210_NVDEC_FIRMWARE "nvidia/tegra210/nvdec.bin"
392 #define NVIDIA_TEGRA_186_NVDEC_FIRMWARE "nvidia/tegra186/nvdec.bin"
400 #define NVIDIA_TEGRA_194_NVDEC_FIRMWARE "nvidia/tegra194/nvdec.bin"
416 { .compatible = "nvidia,tegra210-nvdec", .data = &nvdec_t210_config },
417 { .compatible = "nvidia,tegra186-nvdec", .data = &nvdec_t186_config },
418 { .compatible = "nvidia,tegra194-nvdec", .data = &nvdec_t194_config },
419 { .compatible = "nvidia,tegra234-nvdec", .data = &nvdec_t234_config },
428 struct nvdec *nvdec;
439 nvdec = devm_kzalloc(dev, sizeof(*nvdec), GFP_KERNEL);
440 if (!nvdec)
443 nvdec->config = of_device_get_match_data(dev);
449 nvdec->regs = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
450 if (IS_ERR(nvdec->regs))
451 return PTR_ERR(nvdec->regs);
453 nvdec->clks[0].id = "nvdec";
454 nvdec->num_clks = 1;
456 if (nvdec->config->has_extra_clocks) {
457 nvdec->num_clks = 3;
458 nvdec->clks[1].id = "fuse";
459 nvdec->clks[2].id = "tsec_pka";
462 err = devm_clk_bulk_get(dev, nvdec->num_clks, nvdec->clks);
468 err = clk_set_rate(nvdec->clks[0].clk, ULONG_MAX);
478 if (nvdec->config->has_riscv) {
488 err = tegra_mc_get_carveout_info(mc, 1, &nvdec->carveout_base, NULL);
494 nvdec->reset = devm_reset_control_get_exclusive_released(dev, "nvdec");
495 if (IS_ERR(nvdec->reset)) {
496 dev_err_probe(dev, PTR_ERR(nvdec->reset), "failed to get reset\n");
497 return PTR_ERR(nvdec->reset);
500 nvdec->riscv.dev = dev;
501 nvdec->riscv.regs = nvdec->regs;
503 err = tegra_drm_riscv_read_descriptors(&nvdec->riscv);
507 nvdec->falcon.dev = dev;
508 nvdec->falcon.regs = nvdec->regs;
510 err = falcon_init(&nvdec->falcon);
515 platform_set_drvdata(pdev, nvdec);
517 INIT_LIST_HEAD(&nvdec->client.base.list);
518 nvdec->client.base.ops = &nvdec_client_ops;
519 nvdec->client.base.dev = dev;
520 nvdec->client.base.class = host_class;
521 nvdec->client.base.syncpts = syncpts;
522 nvdec->client.base.num_syncpts = 1;
523 nvdec->dev = dev;
525 INIT_LIST_HEAD(&nvdec->client.list);
526 nvdec->client.version = nvdec->config->version;
527 nvdec->client.ops = &nvdec_ops;
529 err = host1x_client_register(&nvdec->client.base);
542 falcon_exit(&nvdec->falcon);
549 struct nvdec *nvdec = platform_get_drvdata(pdev);
552 host1x_client_unregister(&nvdec->client.base);
553 falcon_exit(&nvdec->falcon);
564 .name = "tegra-nvdec",