Lines Matching defs:value
115 u32 value = readl(hdmi->regs + (offset << 2));
117 trace_hdmi_readl(hdmi->dev, offset, value);
119 return value;
122 static inline void tegra_hdmi_writel(struct tegra_hdmi *hdmi, u32 value,
125 trace_hdmi_writel(hdmi->dev, offset, value);
126 writel(value, hdmi->regs + (offset << 2));
444 u32 value;
454 value = AUDIO_FS_LOW(eight_half - delta) |
456 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_FS(i));
460 static void tegra_hdmi_write_aval(struct tegra_hdmi *hdmi, u32 value)
478 tegra_hdmi_writel(hdmi, value, regs[i].offset);
487 u32 source, value;
533 value = SOR_AUDIO_CNTRL0_INJECT_NULLSMPL;
535 value = 0;
537 value |= source;
539 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_CNTRL0);
546 value = AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0) |
550 value |= source;
552 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_CNTRL0);
558 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_AUDIO_SPARE0);
559 value |= SOR_AUDIO_SPARE0_HBR_ENABLE;
560 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_SPARE0);
577 value = AUDIO_N_RESETF | AUDIO_N_GENERATE_ALTERNATE |
579 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
587 value = SPARE_HW_CTS | SPARE_FORCE_SW_CTS | SPARE_CTS_RESET_VAL(1);
588 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_SPARE);
590 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_AUDIO_N);
591 value &= ~AUDIO_N_RESETF;
592 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
604 u32 value;
606 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
607 value &= ~GENERIC_CTRL_AUDIO;
608 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
613 u32 value;
615 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
616 value |= GENERIC_CTRL_AUDIO;
617 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
623 u32 value;
639 value = SOR_AUDIO_HDA_PRESENSE_VALID | SOR_AUDIO_HDA_PRESENSE_PRESENT;
640 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE);
645 u32 value = 0;
649 value = (value << 8) | ptr[i - 1];
651 return value;
660 u32 value;
681 value = INFOFRAME_HEADER_TYPE(ptr[0]) |
684 tegra_hdmi_writel(hdmi, value, offset);
695 value = tegra_hdmi_subpack(&ptr[i], num);
696 tegra_hdmi_writel(hdmi, value, offset++);
700 value = tegra_hdmi_subpack(&ptr[i + 4], num);
701 tegra_hdmi_writel(hdmi, value, offset++);
730 u32 value;
732 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
733 value &= ~INFOFRAME_CTRL_ENABLE;
734 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
739 u32 value;
741 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
742 value |= INFOFRAME_CTRL_ENABLE;
743 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
779 u32 value;
781 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
782 value &= ~INFOFRAME_CTRL_ENABLE;
783 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
788 u32 value;
790 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
791 value |= INFOFRAME_CTRL_ENABLE;
792 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
816 u32 value;
818 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
819 value &= ~GENERIC_CTRL_ENABLE;
820 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
825 u32 value;
827 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
828 value |= GENERIC_CTRL_ENABLE;
829 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
835 u32 value;
844 value = tegra_hdmi_readl(hdmi, hdmi->config->fuse_override_offset);
845 value |= hdmi->config->fuse_override_value;
846 tegra_hdmi_writel(hdmi, value, hdmi->config->fuse_override_offset);
1166 u32 value;
1176 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1177 value &= ~HDMI_ENABLE;
1178 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1213 u32 value;
1246 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0);
1247 value &= ~SOR_PLL_PDBG;
1248 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_PLL0);
1252 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0);
1253 value &= ~SOR_PLL_PWR;
1254 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_PLL0);
1266 value = PULSE_MODE_NORMAL | PULSE_POLARITY_HIGH | PULSE_QUAL_VACTIVE |
1268 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
1270 value = PULSE_START(pulse_start) | PULSE_END(pulse_start + 8);
1271 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
1273 value = VSYNC_WINDOW_END(0x210) | VSYNC_WINDOW_START(0x200) |
1275 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
1278 value = HDMI_SRC_DISPLAYB;
1280 value = HDMI_SRC_DISPLAYA;
1285 value | ARM_VIDEO_RANGE_FULL,
1289 value | ARM_VIDEO_RANGE_LIMITED,
1293 value = SOR_REFCLK_DIV_INT(div82 >> 2) | SOR_REFCLK_DIV_FRAC(div82);
1294 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_REFCLK);
1313 value = HDMI_CTRL_REKEY(rekey);
1314 value |= HDMI_CTRL_MAX_AC_PACKET((h_sync_width + h_back_porch +
1318 value |= HDMI_CTRL_ENABLE;
1320 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_CTRL);
1345 value = SOR_SEQ_INST_WAIT_TIME(1) |
1352 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(0));
1353 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(8));
1355 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_CSTM);
1356 value &= ~SOR_CSTM_ROTCLK(~0);
1357 value |= SOR_CSTM_ROTCLK(2);
1358 value |= SOR_CSTM_PLLDIV;
1359 value &= ~SOR_CSTM_LVDS_ENABLE;
1360 value &= ~SOR_CSTM_MODE_MASK;
1361 value |= SOR_CSTM_MODE_TMDS;
1362 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_CSTM);
1380 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PWR);
1381 } while (value & SOR_PWR_SETTING_NEW_PENDING);
1383 value = SOR_STATE_ASY_CRCMODE_COMPLETE |
1391 value |= SOR_STATE_ASY_HSYNCPOL_POS;
1394 value |= SOR_STATE_ASY_HSYNCPOL_NEG;
1397 value |= SOR_STATE_ASY_VSYNCPOL_POS;
1400 value |= SOR_STATE_ASY_VSYNCPOL_NEG;
1402 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE2);
1404 value = SOR_STATE_ASY_HEAD_OPMODE_AWAKE | SOR_STATE_ASY_ORMODE_NORMAL;
1405 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE1);
1409 tegra_hdmi_writel(hdmi, value | SOR_STATE_ATTACHED,
1413 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1414 value |= HDMI_ENABLE;
1415 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1767 u32 value;
1769 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_INT_STATUS);
1770 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_INT_STATUS);
1772 if (value & INT_CODEC_SCRATCH0) {
1774 u32 value;
1776 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0);
1778 if (value & SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID) {
1779 format = value & SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK;