Lines Matching defs:pll1
43 u32 pll1;
141 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
156 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
174 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
188 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
202 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
219 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
237 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
256 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
275 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
298 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
316 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
335 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
354 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
838 tegra_hdmi_writel(hdmi, tmds->pll1, HDMI_NV_PDISP_SOR_PLL1);