Lines Matching refs:gr3d
24 #include "gr3d.h"
40 struct gr3d {
53 static inline struct gr3d *to_gr3d(struct tegra_drm_client *client)
55 return container_of(client, struct gr3d, client);
63 struct gr3d *gr3d = to_gr3d(drm);
66 gr3d->channel = host1x_channel_request(client);
67 if (!gr3d->channel)
96 host1x_channel_put(gr3d->channel);
104 struct gr3d *gr3d = to_gr3d(drm);
116 host1x_channel_put(gr3d->channel);
118 gr3d->channel = NULL;
131 struct gr3d *gr3d = to_gr3d(client);
133 context->channel = host1x_channel_get(gr3d->channel);
147 struct gr3d *gr3d = dev_get_drvdata(dev);
160 if (test_bit(offset, gr3d->addr_regs))
195 { .compatible = "nvidia,tegra114-gr3d", .data = &tegra114_gr3d_soc },
196 { .compatible = "nvidia,tegra30-gr3d", .data = &tegra30_gr3d_soc },
197 { .compatible = "nvidia,tegra20-gr3d", .data = &tegra20_gr3d_soc },
310 struct gr3d *gr3d = dev_get_drvdata(dev);
321 if (gr3d->nclocks == 1) {
325 clk = gr3d->clocks[0].clk;
327 for (i = 0; i < gr3d->nclocks; i++) {
328 if (WARN_ON(!gr3d->clocks[i].id))
331 if (!strcmp(gr3d->clocks[i].id, name)) {
332 clk = gr3d->clocks[i].clk;
337 if (WARN_ON(i == gr3d->nclocks))
377 static int gr3d_init_power(struct device *dev, struct gr3d *gr3d)
443 static int gr3d_get_clocks(struct device *dev, struct gr3d *gr3d)
447 err = devm_clk_bulk_get_all(dev, &gr3d->clocks);
452 gr3d->nclocks = err;
454 if (gr3d->nclocks != gr3d->soc->num_clocks) {
455 dev_err(dev, "invalid number of clocks: %u\n", gr3d->nclocks);
462 static int gr3d_get_resets(struct device *dev, struct gr3d *gr3d)
466 gr3d->resets[RST_MC].id = "mc";
467 gr3d->resets[RST_MC2].id = "mc2";
468 gr3d->resets[RST_GR3D].id = "3d";
469 gr3d->resets[RST_GR3D2].id = "3d2";
470 gr3d->nresets = gr3d->soc->num_resets;
473 dev, gr3d->nresets, gr3d->resets);
479 if (WARN_ON(!gr3d->resets[RST_GR3D].rstc) ||
480 WARN_ON(!gr3d->resets[RST_GR3D2].rstc && gr3d->nresets == 4))
489 struct gr3d *gr3d;
493 gr3d = devm_kzalloc(&pdev->dev, sizeof(*gr3d), GFP_KERNEL);
494 if (!gr3d)
497 platform_set_drvdata(pdev, gr3d);
499 gr3d->soc = of_device_get_match_data(&pdev->dev);
505 err = gr3d_get_clocks(&pdev->dev, gr3d);
509 err = gr3d_get_resets(&pdev->dev, gr3d);
513 err = gr3d_init_power(&pdev->dev, gr3d);
517 INIT_LIST_HEAD(&gr3d->client.base.list);
518 gr3d->client.base.ops = &gr3d_client_ops;
519 gr3d->client.base.dev = &pdev->dev;
520 gr3d->client.base.class = HOST1X_CLASS_GR3D;
521 gr3d->client.base.syncpts = syncpts;
522 gr3d->client.base.num_syncpts = 1;
524 INIT_LIST_HEAD(&gr3d->client.list);
525 gr3d->client.version = gr3d->soc->version;
526 gr3d->client.ops = &gr3d_ops;
532 err = host1x_client_register(&gr3d->client.base);
541 set_bit(gr3d_addr_regs[i], gr3d->addr_regs);
548 struct gr3d *gr3d = platform_get_drvdata(pdev);
551 host1x_client_unregister(&gr3d->client.base);
556 struct gr3d *gr3d = dev_get_drvdata(dev);
559 host1x_channel_stop(gr3d->channel);
561 err = reset_control_bulk_assert(gr3d->nresets, gr3d->resets);
575 clk_bulk_disable_unprepare(gr3d->nclocks, gr3d->clocks);
576 reset_control_bulk_release(gr3d->nresets, gr3d->resets);
583 struct gr3d *gr3d = dev_get_drvdata(dev);
586 err = reset_control_bulk_acquire(gr3d->nresets, gr3d->resets);
592 err = clk_bulk_prepare_enable(gr3d->nclocks, gr3d->clocks);
598 err = reset_control_bulk_deassert(gr3d->nresets, gr3d->resets);
611 clk_bulk_disable_unprepare(gr3d->nclocks, gr3d->clocks);
613 reset_control_bulk_release(gr3d->nresets, gr3d->resets);
626 .name = "tegra-gr3d",