Lines Matching defs:value
109 u32 value = readl(dsi->regs + (offset << 2));
111 trace_dsi_readl(dsi->dev, offset, value);
113 return value;
116 static inline void tegra_dsi_writel(struct tegra_dsi *dsi, u32 value,
119 trace_dsi_writel(dsi->dev, offset, value);
120 writel(value, dsi->regs + (offset << 2));
361 u32 value;
363 value = DSI_TIMING_FIELD(timing->hsexit, period, 1) << 24 |
367 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_0);
369 value = DSI_TIMING_FIELD(timing->clktrail, period, 1) << 24 |
373 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_1);
375 value = DSI_TIMING_FIELD(timing->clkprepare, period, 1) << 16 |
378 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_2);
380 value = DSI_TIMING_FIELD(timing->taget, period, 1) << 16 |
383 tegra_dsi_writel(dsi, value, DSI_BTA_TIMING);
446 u32 value;
451 value = DSI_GANGED_MODE_CONTROL_ENABLE;
452 tegra_dsi_writel(dsi, value, DSI_GANGED_MODE_CONTROL);
457 u32 value;
459 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
460 value |= DSI_POWER_CONTROL_ENABLE;
461 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
484 u32 value;
506 value = DSI_CONTROL_CHANNEL(0) |
510 tegra_dsi_writel(dsi, value, DSI_CONTROL);
514 value = DSI_HOST_CONTROL_HS;
515 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
517 value = tegra_dsi_readl(dsi, DSI_CONTROL);
520 value |= DSI_CONTROL_HS_CLK_CTRL;
522 value &= ~DSI_CONTROL_TX_TRIG(3);
526 value &= ~DSI_CONTROL_DCS_ENABLE;
528 value |= DSI_CONTROL_DCS_ENABLE;
530 value |= DSI_CONTROL_VIDEO_ENABLE;
531 value &= ~DSI_CONTROL_HOST_ENABLE;
532 tegra_dsi_writel(dsi, value, DSI_CONTROL);
585 value = MIPI_DCS_WRITE_MEMORY_START << 8 |
587 tegra_dsi_writel(dsi, value, DSI_DCS_CMDS);
602 value = bclk - bclk_ganged + delay + 20;
605 value = 8 * mul / div;
608 tegra_dsi_writel(dsi, value, DSI_SOL_DELAY);
626 u32 value;
631 value = tegra_dsi_readl(dsi, DSI_STATUS);
632 if (value & DSI_STATUS_IDLE)
643 u32 value;
645 value = tegra_dsi_readl(dsi, DSI_CONTROL);
646 value &= ~DSI_CONTROL_VIDEO_ENABLE;
647 tegra_dsi_writel(dsi, value, DSI_CONTROL);
662 u32 value;
664 value = DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0);
665 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0);
672 u32 value;
688 value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) |
691 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2);
693 value = DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) |
695 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_3);
708 u32 value;
712 value = DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(timeout);
713 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_0);
717 value = DSI_TIMEOUT_PR(timeout) | DSI_TIMEOUT_TA(0x2000);
718 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_1);
720 value = DSI_TALLY_TA(0) | DSI_TALLY_LRX(0) | DSI_TALLY_HTX(0);
721 tegra_dsi_writel(dsi, value, DSI_TO_TALLY);
729 u32 value;
736 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
737 value &= ~DSI_POWER_CONTROL_ENABLE;
738 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
748 u32 value;
750 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
751 value &= ~DSI_POWER_CONTROL_ENABLE;
752 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
756 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
757 value |= DSI_POWER_CONTROL_ENABLE;
758 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
762 value = tegra_dsi_readl(dsi, DSI_TRIGGER);
763 if (value)
846 u32 value;
859 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
860 value &= ~DSI_ENABLE;
861 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
912 u32 value;
919 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
921 if (value & DSI_POWER_CONTROL_ENABLE)
946 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
947 value |= DSI_ENABLE;
948 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1014 * correct value.
1220 u32 value;
1223 value = tegra_dsi_readl(dsi, DSI_RD_DATA);
1225 switch (value & 0x3f) {
1227 errors = (value >> 8) & 0xffff;
1237 rx[0] = (value >> 8) & 0xff;
1242 rx[0] = (value >> 8) & 0xff;
1243 rx[1] = (value >> 16) & 0xff;
1248 size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff);
1252 size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff);
1257 value & 0x3f);
1267 value = tegra_dsi_readl(dsi, DSI_RD_DATA);
1270 rx[j + k] = (value >> (k << 3)) & 0xff;
1284 u32 value = tegra_dsi_readl(dsi, DSI_TRIGGER);
1285 if ((value & DSI_TRIGGER_HOST) == 0)
1301 u32 value = tegra_dsi_readl(dsi, DSI_STATUS);
1302 u8 count = value & 0x1f;
1319 u32 value;
1322 value = 0;
1325 value |= buf[j + i] << (i << 3);
1327 tegra_dsi_writel(dsi, value, DSI_WR_DATA);
1339 u32 value;
1352 value = tegra_dsi_readl(dsi, DSI_STATUS);
1353 if (value & (DSI_STATUS_UNDERFLOW | DSI_STATUS_OVERFLOW)) {
1354 value = DSI_HOST_CONTROL_FIFO_RESET;
1355 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
1359 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
1360 value |= DSI_POWER_CONTROL_ENABLE;
1361 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
1365 value = DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST |
1369 value |= DSI_HOST_CONTROL_HS;
1376 value |= DSI_HOST_CONTROL_FIFO_SEL;
1378 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
1386 value = tegra_dsi_readl(dsi, DSI_HOST_CONTROL);
1387 value |= DSI_HOST_CONTROL_PKT_BTA;
1388 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
1391 value = DSI_CONTROL_LANES(0) | DSI_CONTROL_HOST_ENABLE;
1392 tegra_dsi_writel(dsi, value, DSI_CONTROL);
1395 value = header[2] << 16 | header[1] << 8 | header[0];
1396 tegra_dsi_writel(dsi, value, DSI_WR_DATA);
1415 value = tegra_dsi_readl(dsi, DSI_RD_DATA);
1416 switch (value) {
1430 dev_err(dsi->dev, "unknown status: %08x\n", value);