Lines Matching defs:timing
36 struct mipi_dphy_timing timing;
359 const struct mipi_dphy_timing *timing)
363 value = DSI_TIMING_FIELD(timing->hsexit, period, 1) << 24 |
364 DSI_TIMING_FIELD(timing->hstrail, period, 0) << 16 |
365 DSI_TIMING_FIELD(timing->hszero, period, 3) << 8 |
366 DSI_TIMING_FIELD(timing->hsprepare, period, 1);
369 value = DSI_TIMING_FIELD(timing->clktrail, period, 1) << 24 |
370 DSI_TIMING_FIELD(timing->clkpost, period, 1) << 16 |
371 DSI_TIMING_FIELD(timing->clkzero, period, 1) << 8 |
372 DSI_TIMING_FIELD(timing->lpx, period, 1);
375 value = DSI_TIMING_FIELD(timing->clkprepare, period, 1) << 16 |
376 DSI_TIMING_FIELD(timing->clkpre, period, 1) << 8 |
380 value = DSI_TIMING_FIELD(timing->taget, period, 1) << 16 |
381 DSI_TIMING_FIELD(timing->tasure, period, 1) << 8 |
382 DSI_TIMING_FIELD(timing->tago, period, 1);
386 tegra_dsi_set_phy_timing(dsi->slave, period, timing);
935 * The D-PHY timing fields are expressed in byte-clock cycles, so
938 tegra_dsi_set_phy_timing(dsi, state->period * 8, &state->timing);
1001 err = mipi_dphy_timing_get_default(&state->timing, state->period);
1005 err = mipi_dphy_timing_validate(&state->timing, state->period);
1007 dev_err(dsi->dev, "failed to validate D-PHY timing: %d\n", err);