Lines Matching defs:rate
1867 unsigned long rate, pstate;
1874 /* calculate actual pixel clock rate which depends on internal divider */
1875 rate = DIV_ROUND_UP(clk_get_rate(dc->clk) * 2, state->div + 2);
1877 /* find suitable OPP for the rate */
1878 opp = dev_pm_opp_find_freq_ceil(dc->dev, &rate);
1881 * Very high resolution modes may results in a clock rate that is
1886 opp = dev_pm_opp_find_freq_floor(dc->dev, &rate);
1890 rate, opp);
1898 * The minimum core voltage depends on the pixel clock rate (which
1900 * rate of the display controller clock. This is why we're not using
1920 * Outputs may not want to change the parent clock rate. This is only
1924 * which is shared with other peripherals. Changing the clock rate
1931 "failed to set clock rate to %lu Hz\n",
1940 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk),