Lines Matching refs:tcon
84 static void sun4i_tcon_channel_set_status(struct sun4i_tcon *tcon, int channel,
91 WARN_ON(!tcon->quirks->has_channel_0);
92 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
95 clk = tcon->dclk;
98 WARN_ON(!tcon->quirks->has_channel_1);
99 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
102 clk = tcon->sclk1;
118 static void sun4i_tcon_setup_lvds_phy(struct sun4i_tcon *tcon,
121 regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
130 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA1_REG,
134 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA1_REG,
137 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
142 static void sun6i_tcon_setup_lvds_phy(struct sun4i_tcon *tcon,
147 regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
154 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
159 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
168 regmap_write_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
173 static void sun4i_tcon_lvds_set_status(struct sun4i_tcon *tcon,
178 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG,
181 if (tcon->quirks->setup_lvds_phy)
182 tcon->quirks->setup_lvds_phy(tcon, encoder);
184 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG,
189 void sun4i_tcon_set_status(struct sun4i_tcon *tcon,
214 sun4i_tcon_lvds_set_status(tcon, encoder, false);
216 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
221 sun4i_tcon_lvds_set_status(tcon, encoder, true);
223 sun4i_tcon_channel_set_status(tcon, channel, enabled);
226 void sun4i_tcon_enable_vblank(struct sun4i_tcon *tcon, bool enable)
239 regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG, mask, val);
252 struct sun4i_tcon *tcon;
254 list_for_each_entry(tcon, &drv->tcon_list, list)
255 if (tcon->id == 0)
256 return tcon;
264 static void sun4i_tcon_set_mux(struct sun4i_tcon *tcon, int channel,
269 if (tcon->quirks->set_mux)
270 ret = tcon->quirks->set_mux(tcon, encoder);
294 static void sun4i_tcon0_mode_set_dithering(struct sun4i_tcon *tcon,
310 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PR_REG, 0x11111111);
311 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PG_REG, 0x11111111);
312 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PB_REG, 0x11111111);
313 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LR_REG, 0x11111111);
314 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LG_REG, 0x11111111);
315 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LB_REG, 0x11111111);
316 regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL0_REG, 0x01010000);
317 regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL1_REG, 0x15151111);
318 regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL2_REG, 0x57575555);
319 regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL3_REG, 0x7f7f7777);
343 regmap_write(tcon->regs, SUN4I_TCON_FRM_CTL_REG, val);
346 static void sun4i_tcon0_mode_set_cpu(struct sun4i_tcon *tcon,
361 tcon->dclk_min_div = SUN6I_DSI_TCON_DIV;
362 tcon->dclk_max_div = SUN6I_DSI_TCON_DIV;
363 clk_set_rate(tcon->dclk, mode->crtc_clock * 1000 * (bpp / lanes)
367 regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
372 sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder));
374 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
378 regmap_write(tcon->regs, SUN4I_TCON_ECC_FIFO_REG,
381 regmap_write(tcon->regs, SUN4I_TCON0_CPU_IF_REG,
393 regmap_read(tcon->regs, SUN4I_TCON0_DCLK_REG, &tcon_div);
398 regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI0_REG,
402 regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI1_REG,
408 regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI2_REG,
416 regmap_write(tcon->regs, SUN4I_TCON_SAFE_PERIOD_REG,
421 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG,
425 static void sun4i_tcon0_mode_set_lvds(struct sun4i_tcon *tcon,
433 WARN_ON(!tcon->quirks->has_channel_0);
435 tcon->dclk_min_div = 7;
436 tcon->dclk_max_div = 7;
437 clk_set_rate(tcon->dclk, mode->crtc_clock * 1000);
440 regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
445 sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder));
449 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
462 regmap_write(tcon->regs, SUN4I_TCON0_BASIC1_REG,
475 regmap_write(tcon->regs, SUN4I_TCON0_BASIC2_REG,
485 regmap_write(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, reg);
494 regmap_write(tcon->regs, SUN4I_TCON0_IO_POL_REG, val);
497 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
502 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 0xe0000000);
505 static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon,
515 WARN_ON(!tcon->quirks->has_channel_0);
517 tcon->dclk_min_div = tcon->quirks->dclk_min_div;
518 tcon->dclk_max_div = 127;
519 clk_set_rate(tcon->dclk, mode->crtc_clock * 1000);
522 regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
527 sun4i_tcon0_mode_set_dithering(tcon, connector);
531 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
544 regmap_write(tcon->regs, SUN4I_TCON0_BASIC1_REG,
557 regmap_write(tcon->regs, SUN4I_TCON0_BASIC2_REG,
565 regmap_write(tcon->regs, SUN4I_TCON0_BASIC3_REG,
582 regmap_update_bits(tcon->regs, SUN4I_TCON0_IO_POL_REG,
590 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
595 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 0);
598 static void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon,
605 WARN_ON(!tcon->quirks->has_channel_1);
608 clk_set_rate(tcon->sclk1, mode->crtc_clock * 1000);
612 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
621 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
626 regmap_write(tcon->regs, SUN4I_TCON1_BASIC0_REG,
631 regmap_write(tcon->regs, SUN4I_TCON1_BASIC1_REG,
636 regmap_write(tcon->regs, SUN4I_TCON1_BASIC2_REG,
644 regmap_write(tcon->regs, SUN4I_TCON1_BASIC3_REG,
670 regmap_write(tcon->regs, SUN4I_TCON1_BASIC4_REG,
678 regmap_write(tcon->regs, SUN4I_TCON1_BASIC5_REG,
683 if (tcon->quirks->polarity_in_ch0) {
692 regmap_write(tcon->regs, SUN4I_TCON0_IO_POL_REG, val);
703 regmap_write(tcon->regs, SUN4I_TCON1_IO_POL_REG, val);
707 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
712 void sun4i_tcon_mode_set(struct sun4i_tcon *tcon,
719 sun4i_tcon0_mode_set_cpu(tcon, encoder, mode);
722 sun4i_tcon0_mode_set_lvds(tcon, encoder, mode);
725 sun4i_tcon0_mode_set_rgb(tcon, encoder, mode);
726 sun4i_tcon_set_mux(tcon, 0, encoder);
730 sun4i_tcon1_mode_set(tcon, mode);
731 sun4i_tcon_set_mux(tcon, 1, encoder);
755 struct sun4i_tcon *tcon = private;
756 struct drm_device *drm = tcon->drm;
757 struct sun4i_crtc *scrtc = tcon->crtc;
761 regmap_read(tcon->regs, SUN4I_TCON_GINT0_REG, &status);
772 regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG,
785 struct sun4i_tcon *tcon)
787 tcon->clk = devm_clk_get_enabled(dev, "ahb");
788 if (IS_ERR(tcon->clk)) {
790 return PTR_ERR(tcon->clk);
793 if (tcon->quirks->has_channel_0) {
794 tcon->sclk0 = devm_clk_get_enabled(dev, "tcon-ch0");
795 if (IS_ERR(tcon->sclk0)) {
797 return PTR_ERR(tcon->sclk0);
801 if (tcon->quirks->has_channel_1) {
802 tcon->sclk1 = devm_clk_get(dev, "tcon-ch1");
803 if (IS_ERR(tcon->sclk1)) {
805 return PTR_ERR(tcon->sclk1);
813 struct sun4i_tcon *tcon)
823 dev_name(dev), tcon);
840 struct sun4i_tcon *tcon)
849 tcon->regs = devm_regmap_init_mmio(dev, regs,
851 if (IS_ERR(tcon->regs)) {
853 return PTR_ERR(tcon->regs);
857 regmap_write(tcon->regs, SUN4I_TCON_GCTL_REG, 0);
858 regmap_write(tcon->regs, SUN4I_TCON_GINT0_REG, 0);
859 regmap_write(tcon->regs, SUN4I_TCON_GINT1_REG, 0);
862 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, ~0);
863 regmap_write(tcon->regs, SUN4I_TCON1_IO_TRI_REG, ~0);
871 * the of_graph upwards to find the backend our tcon is connected to,
1116 struct sun4i_tcon *tcon;
1127 tcon = devm_kzalloc(dev, sizeof(*tcon), GFP_KERNEL);
1128 if (!tcon)
1130 dev_set_drvdata(dev, tcon);
1131 tcon->drm = drm;
1132 tcon->dev = dev;
1133 tcon->id = engine->id;
1134 tcon->quirks = of_device_get_match_data(dev);
1136 tcon->lcd_rst = devm_reset_control_get(dev, "lcd");
1137 if (IS_ERR(tcon->lcd_rst)) {
1139 return PTR_ERR(tcon->lcd_rst);
1142 if (tcon->quirks->needs_edp_reset) {
1157 ret = reset_control_reset(tcon->lcd_rst);
1163 if (tcon->quirks->supports_lvds) {
1171 tcon->lvds_rst = devm_reset_control_get_optional(dev, "lvds");
1172 if (IS_ERR(tcon->lvds_rst)) {
1174 return PTR_ERR(tcon->lvds_rst);
1175 } else if (tcon->lvds_rst) {
1177 reset_control_reset(tcon->lvds_rst);
1189 if (tcon->quirks->has_lvds_alt) {
1190 tcon->lvds_pll = devm_clk_get(dev, "lvds-alt");
1191 if (IS_ERR(tcon->lvds_pll)) {
1192 if (PTR_ERR(tcon->lvds_pll) == -ENOENT) {
1196 return PTR_ERR(tcon->lvds_pll);
1204 (tcon->quirks->has_lvds_alt && !has_lvds_alt)) {
1215 ret = sun4i_tcon_init_clocks(dev, tcon);
1221 ret = sun4i_tcon_init_regmap(dev, tcon);
1227 if (tcon->quirks->has_channel_0) {
1228 ret = sun4i_dclk_create(dev, tcon);
1235 ret = sun4i_tcon_init_irq(dev, tcon);
1241 tcon->crtc = sun4i_crtc_init(drm, engine, tcon);
1242 if (IS_ERR(tcon->crtc)) {
1244 ret = PTR_ERR(tcon->crtc);
1248 if (tcon->quirks->has_channel_0) {
1257 ret = sun4i_lvds_init(drm, tcon);
1261 ret = sun4i_rgb_init(drm, tcon);
1268 if (tcon->quirks->needs_de_be_mux) {
1279 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
1281 tcon->id);
1282 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
1284 tcon->id);
1287 list_add_tail(&tcon->list, &drv->tcon_list);
1292 if (tcon->quirks->has_channel_0)
1293 sun4i_dclk_free(tcon);
1295 reset_control_assert(tcon->lcd_rst);
1302 struct sun4i_tcon *tcon = dev_get_drvdata(dev);
1304 list_del(&tcon->list);
1305 if (tcon->quirks->has_channel_0)
1306 sun4i_dclk_free(tcon);
1340 static int sun4i_a10_tcon_set_mux(struct sun4i_tcon *tcon,
1359 0x3 << shift, tcon->id << shift);
1364 static int sun5i_a13_tcon_set_mux(struct sun4i_tcon *tcon,
1377 return regmap_write(tcon->regs, SUN4I_TCON_MUX_CTRL_REG, val);
1380 static int sun6i_tcon_set_mux(struct sun4i_tcon *tcon,
1400 0x3 << shift, tcon->id << shift);
1405 static int sun8i_r40_tcon_tv_set_mux(struct sun4i_tcon *tcon,
1414 port = of_graph_get_port_by_id(tcon->dev->of_node, 0);
1421 remote = of_graph_get_remote_node(tcon->dev->of_node, 0, -1);
1440 ret = sun8i_tcon_top_de_config(&pdev->dev, tcon->id, id);
1547 { .compatible = "allwinner,sun4i-a10-tcon", .data = &sun4i_a10_quirks },
1548 { .compatible = "allwinner,sun5i-a13-tcon", .data = &sun5i_a13_quirks },
1549 { .compatible = "allwinner,sun6i-a31-tcon", .data = &sun6i_a31_quirks },
1550 { .compatible = "allwinner,sun6i-a31s-tcon", .data = &sun6i_a31s_quirks },
1551 { .compatible = "allwinner,sun7i-a20-tcon", .data = &sun7i_a20_quirks },
1554 { .compatible = "allwinner,sun8i-a23-tcon", .data = &sun8i_a33_quirks },
1555 { .compatible = "allwinner,sun8i-a33-tcon", .data = &sun8i_a33_quirks },
1556 { .compatible = "allwinner,sun8i-a83t-tcon-lcd", .data = &sun8i_a83t_lcd_quirks },
1557 { .compatible = "allwinner,sun8i-a83t-tcon-tv", .data = &sun8i_a83t_tv_quirks },
1558 { .compatible = "allwinner,sun8i-r40-tcon-tv", .data = &sun8i_r40_tv_quirks },
1559 { .compatible = "allwinner,sun8i-v3s-tcon", .data = &sun8i_v3s_quirks },
1560 { .compatible = "allwinner,sun9i-a80-tcon-lcd", .data = &sun9i_a80_tcon_lcd_quirks },
1561 { .compatible = "allwinner,sun9i-a80-tcon-tv", .data = &sun9i_a80_tcon_tv_quirks },
1562 { .compatible = "allwinner,sun20i-d1-tcon-lcd", .data = &sun20i_d1_lcd_quirks },
1563 { .compatible = "allwinner,sun20i-d1-tcon-tv", .data = &sun8i_r40_tv_quirks },
1573 .name = "sun4i-tcon",