Lines Matching defs:ldev
60 #define LAY_OFS (ldev->caps.layer_ofs)
86 #define LTDC_L1C0R (ldev->caps.layer_regs[0]) /* L1 configuration 0 */
87 #define LTDC_L1C1R (ldev->caps.layer_regs[1]) /* L1 configuration 1 */
88 #define LTDC_L1RCR (ldev->caps.layer_regs[2]) /* L1 reload control */
89 #define LTDC_L1CR (ldev->caps.layer_regs[3]) /* L1 control register */
90 #define LTDC_L1WHPCR (ldev->caps.layer_regs[4]) /* L1 window horizontal position configuration */
91 #define LTDC_L1WVPCR (ldev->caps.layer_regs[5]) /* L1 window vertical position configuration */
92 #define LTDC_L1CKCR (ldev->caps.layer_regs[6]) /* L1 color keying configuration */
93 #define LTDC_L1PFCR (ldev->caps.layer_regs[7]) /* L1 pixel format configuration */
94 #define LTDC_L1CACR (ldev->caps.layer_regs[8]) /* L1 constant alpha configuration */
95 #define LTDC_L1DCCR (ldev->caps.layer_regs[9]) /* L1 default color configuration */
96 #define LTDC_L1BFCR (ldev->caps.layer_regs[10]) /* L1 blending factors configuration */
97 #define LTDC_L1BLCR (ldev->caps.layer_regs[11]) /* L1 burst length configuration */
98 #define LTDC_L1PCR (ldev->caps.layer_regs[12]) /* L1 planar configuration */
99 #define LTDC_L1CFBAR (ldev->caps.layer_regs[13]) /* L1 color frame buffer address */
100 #define LTDC_L1CFBLR (ldev->caps.layer_regs[14]) /* L1 color frame buffer length */
101 #define LTDC_L1CFBLNR (ldev->caps.layer_regs[15]) /* L1 color frame buffer line number */
102 #define LTDC_L1AFBA0R (ldev->caps.layer_regs[16]) /* L1 auxiliary frame buffer address 0 */
103 #define LTDC_L1AFBA1R (ldev->caps.layer_regs[17]) /* L1 auxiliary frame buffer address 1 */
104 #define LTDC_L1AFBLR (ldev->caps.layer_regs[18]) /* L1 auxiliary frame buffer length */
105 #define LTDC_L1AFBLNR (ldev->caps.layer_regs[19]) /* L1 auxiliary frame buffer line number */
106 #define LTDC_L1CLUTWR (ldev->caps.layer_regs[20]) /* L1 CLUT write */
107 #define LTDC_L1CYR0R (ldev->caps.layer_regs[21]) /* L1 Conversion YCbCr RGB 0 */
108 #define LTDC_L1CYR1R (ldev->caps.layer_regs[22]) /* L1 Conversion YCbCr RGB 1 */
109 #define LTDC_L1FPF0R (ldev->caps.layer_regs[23]) /* L1 Flexible Pixel Format 0 */
110 #define LTDC_L1FPF1R (ldev->caps.layer_regs[24]) /* L1 Flexible Pixel Format 1 */
554 struct ltdc_device *ldev = plane_to_ltdc(plane);
595 regmap_write(ldev->regmap, LTDC_L1FPF0R + lofs,
598 regmap_write(ldev->regmap, LTDC_L1FPF1R + lofs,
616 struct ltdc_device *ldev = plane_to_ltdc(plane);
657 regmap_write(ldev->regmap, LTDC_L1PCR + lofs, val);
662 struct ltdc_device *ldev = plane_to_ltdc(plane);
681 regmap_write(ldev->regmap, LTDC_L1CYR0R + lofs,
683 regmap_write(ldev->regmap, LTDC_L1CYR1R + lofs,
687 static inline void ltdc_irq_crc_handle(struct ltdc_device *ldev,
693 if (ldev->crc_skip_count < CRC_SKIP_FRAMES) {
694 ldev->crc_skip_count++;
699 ret = regmap_read(ldev->regmap, LTDC_CCRCR, &crc);
710 struct ltdc_device *ldev = ddev->dev_private;
714 if (ldev->irq_status & ISR_LIF) {
718 if (ldev->crc_active)
719 ltdc_irq_crc_handle(ldev, crtc);
722 mutex_lock(&ldev->err_lock);
723 if (ldev->irq_status & ISR_TERRIF)
724 ldev->transfer_err++;
725 if (ldev->irq_status & ISR_FUEIF)
726 ldev->fifo_err++;
727 if (ldev->irq_status & ISR_FUWIF)
728 ldev->fifo_warn++;
729 mutex_unlock(&ldev->err_lock);
737 struct ltdc_device *ldev = ddev->dev_private;
744 ldev->irq_status = readl_relaxed(ldev->regs + LTDC_ISR);
745 writel_relaxed(ldev->irq_status, ldev->regs + LTDC_ICR);
756 struct ltdc_device *ldev = crtc_to_ltdc(crtc);
769 regmap_write(ldev->regmap, LTDC_L1CLUTWR, val);
776 struct ltdc_device *ldev = crtc_to_ltdc(crtc);
784 regmap_write(ldev->regmap, LTDC_BCCR, BCCR_BCBLACK);
787 regmap_set_bits(ldev->regmap, LTDC_IER, IER_FUWIE | IER_FUEIE | IER_RRIE | IER_TERRIE);
790 if (!ldev->caps.plane_reg_shadow)
791 regmap_set_bits(ldev->regmap, LTDC_SRCR, SRCR_VBR);
799 struct ltdc_device *ldev = crtc_to_ltdc(crtc);
808 for (layer_index = 0; layer_index < ldev->caps.nb_layers; layer_index++)
809 regmap_write_bits(ldev->regmap, LTDC_L1CR + layer_index * LAY_OFS,
813 regmap_clear_bits(ldev->regmap, LTDC_IER, IER_FUWIE | IER_FUEIE | IER_RRIE | IER_TERRIE);
816 if (!ldev->caps.plane_reg_shadow)
817 regmap_set_bits(ldev->regmap, LTDC_SRCR, SRCR_IMR);
822 mutex_lock(&ldev->err_lock);
823 ldev->transfer_err = 0;
824 ldev->fifo_err = 0;
825 ldev->fifo_warn = 0;
826 mutex_unlock(&ldev->err_lock);
835 struct ltdc_device *ldev = crtc_to_ltdc(crtc);
841 result = clk_round_rate(ldev->pixel_clk, target);
846 if (result > ldev->caps.pad_max_freq_hz)
874 struct ltdc_device *ldev = crtc_to_ltdc(crtc);
877 if (clk_set_rate(ldev->pixel_clk, rate) < 0) {
882 adjusted_mode->clock = clk_get_rate(ldev->pixel_clk) / 1000;
892 struct ltdc_device *ldev = crtc_to_ltdc(crtc);
980 regmap_update_bits(ldev->regmap, LTDC_GCR,
985 regmap_update_bits(ldev->regmap, LTDC_SSCR, SSCR_VSH | SSCR_HSW, val);
989 regmap_update_bits(ldev->regmap, LTDC_BPCR, BPCR_AVBP | BPCR_AHBP, val);
993 regmap_update_bits(ldev->regmap, LTDC_AWCR, AWCR_AAW | AWCR_AAH, val);
997 regmap_update_bits(ldev->regmap, LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val);
999 regmap_write(ldev->regmap, LTDC_LIPCR, (accum_act_h + 1));
1002 if (ldev->caps.ycbcr_output) {
1018 regmap_write(ldev->regmap, LTDC_EDCR, EDCR_OCYEN | val);
1022 regmap_write(ldev->regmap, LTDC_EDCR, EDCR_OCYEN | EDCR_OCYCO | val);
1026 regmap_write(ldev->regmap, LTDC_EDCR, 0);
1035 struct ltdc_device *ldev = crtc_to_ltdc(crtc);
1044 if (!ldev->caps.plane_reg_shadow)
1045 regmap_set_bits(ldev->regmap, LTDC_SRCR, SRCR_VBR);
1066 struct ltdc_device *ldev = ddev->dev_private;
1087 regmap_read(ldev->regmap, LTDC_CPSR, &line);
1089 regmap_read(ldev->regmap, LTDC_BPCR, &vactive_start);
1091 regmap_read(ldev->regmap, LTDC_AWCR, &vactive_end);
1093 regmap_read(ldev->regmap, LTDC_TWCR, &vtotal);
1124 struct ltdc_device *ldev = crtc_to_ltdc(crtc);
1130 regmap_set_bits(ldev->regmap, LTDC_IER, IER_LIE);
1139 struct ltdc_device *ldev = crtc_to_ltdc(crtc);
1142 regmap_clear_bits(ldev->regmap, LTDC_IER, IER_LIE);
1147 struct ltdc_device *ldev;
1155 ldev = crtc_to_ltdc(crtc);
1158 ldev->crc_active = true;
1159 ret = regmap_set_bits(ldev->regmap, LTDC_GCR, GCR_CRCEN);
1161 ldev->crc_active = false;
1162 ret = regmap_clear_bits(ldev->regmap, LTDC_GCR, GCR_CRCEN);
1167 ldev->crc_skip_count = 0;
1193 struct ltdc_device *ldev = crtc_to_ltdc(crtc);
1195 drm_printf(p, "\ttransfer_error=%d\n", ldev->transfer_err);
1196 drm_printf(p, "\tfifo_underrun_error=%d\n", ldev->fifo_err);
1197 drm_printf(p, "\tfifo_underrun_warning=%d\n", ldev->fifo_warn);
1198 drm_printf(p, "\tfifo_underrun_threshold=%d\n", ldev->fifo_threshold);
1263 struct ltdc_device *ldev = plane_to_ltdc(plane);
1294 regmap_read(ldev->regmap, LTDC_BPCR, &bpcr);
1301 regmap_write_bits(ldev->regmap, LTDC_L1WHPCR + lofs,
1306 regmap_write_bits(ldev->regmap, LTDC_L1WVPCR + lofs,
1312 if (ldev->caps.pix_fmt_hw[val] == pf)
1316 if (ldev->caps.pix_fmt_flex && val == NB_PF)
1324 regmap_write_bits(ldev->regmap, LTDC_L1PFCR + lofs, LXPFCR_PF, val);
1328 regmap_write_bits(ldev->regmap, LTDC_L1CACR + lofs, LXCACR_CONSTA, val);
1336 if (ldev->caps.non_alpha_only_l1 &&
1340 if (ldev->caps.dynamic_zorder) {
1342 regmap_write_bits(ldev->regmap, LTDC_L1BFCR + lofs,
1345 regmap_write_bits(ldev->regmap, LTDC_L1BFCR + lofs,
1359 regmap_write(ldev->regmap, LTDC_L1CFBAR + lofs, paddr);
1363 (x1 - x0 + 1) + (ldev->caps.bus_width >> 3) - 1;
1372 regmap_write_bits(ldev->regmap, LTDC_L1CFBLR + lofs, LXCFBLR_CFBLL | LXCFBLR_CFBP, val);
1376 regmap_write_bits(ldev->regmap, LTDC_L1CFBLNR + lofs, LXCFBLNR_CFBLN, line_number);
1378 if (ldev->caps.ycbcr_input) {
1392 regmap_write(ldev->regmap, LTDC_L1AFBA0R + lofs, paddr1);
1409 regmap_write(ldev->regmap, LTDC_L1AFBA0R + lofs, paddr1);
1410 regmap_write(ldev->regmap, LTDC_L1AFBA1R + lofs, paddr2);
1427 regmap_write(ldev->regmap, LTDC_L1AFBA0R + lofs, paddr1);
1428 regmap_write(ldev->regmap, LTDC_L1AFBA1R + lofs, paddr2);
1447 (ldev->caps.bus_width >> 3) - 1;
1451 regmap_write(ldev->regmap, LTDC_L1AFBLR + lofs, val);
1455 regmap_write(ldev->regmap, LTDC_L1AFBLNR + lofs, val);
1465 regmap_write(ldev->regmap, LTDC_L1PCR + lofs, 0);
1477 regmap_write_bits(ldev->regmap, LTDC_L1CR + lofs, LXCR_LEN | LXCR_CLUTEN | LXCR_HMEN, val);
1480 if (ldev->caps.plane_reg_shadow)
1481 regmap_write_bits(ldev->regmap, LTDC_L1RCR + lofs,
1484 ldev->plane_fpsi[plane->index].counter++;
1486 mutex_lock(&ldev->err_lock);
1487 if (ldev->transfer_err) {
1488 DRM_WARN("ltdc transfer error: %d\n", ldev->transfer_err);
1489 ldev->transfer_err = 0;
1492 if (ldev->caps.fifo_threshold) {
1493 if (ldev->fifo_err) {
1495 ldev->fifo_err = 0;
1498 if (ldev->fifo_warn >= ldev->fifo_threshold) {
1500 ldev->fifo_warn = 0;
1503 mutex_unlock(&ldev->err_lock);
1511 struct ltdc_device *ldev = plane_to_ltdc(plane);
1515 regmap_write_bits(ldev->regmap, LTDC_L1CR + lofs, LXCR_LEN | LXCR_CLUTEN | LXCR_HMEN, 0);
1518 if (ldev->caps.plane_reg_shadow)
1519 regmap_write_bits(ldev->regmap, LTDC_L1RCR + lofs,
1530 struct ltdc_device *ldev = plane_to_ltdc(plane);
1531 struct fps_info *fpsi = &ldev->plane_fpsi[plane->index];
1566 struct ltdc_device *ldev = ddev->dev_private;
1578 formats = devm_kzalloc(dev, (ldev->caps.pix_fmt_nb +
1584 for (i = 0; i < ldev->caps.pix_fmt_nb; i++) {
1585 drm_fmt = ldev->caps.pix_fmt_drm[i];
1588 if (ldev->caps.non_alpha_only_l1)
1597 if (ldev->caps.ycbcr_input) {
1598 regmap_read(ldev->regmap, LTDC_L1C1R + lofs, &val);
1626 if (ldev->caps.ycbcr_input) {
1657 struct ltdc_device *ldev = ddev->dev_private;
1669 if (ldev->caps.dynamic_zorder)
1670 drm_plane_create_zpos_property(primary, 0, 0, ldev->caps.nb_layers - 1);
1674 if (ldev->caps.plane_rotation)
1679 if (ldev->caps.crc)
1698 for (i = 1; i < ldev->caps.nb_layers; i++) {
1705 if (ldev->caps.dynamic_zorder)
1706 drm_plane_create_zpos_property(overlay, i, 0, ldev->caps.nb_layers - 1);
1710 if (ldev->caps.plane_rotation)
1725 struct ltdc_device *ldev = ddev->dev_private;
1730 regmap_clear_bits(ldev->regmap, LTDC_GCR, GCR_LTDCEN);
1739 struct ltdc_device *ldev = ddev->dev_private;
1744 if (ldev->caps.fifo_threshold)
1745 regmap_write(ldev->regmap, LTDC_FUT, ldev->fifo_threshold);
1748 regmap_set_bits(ldev->regmap, LTDC_GCR, GCR_LTDCEN);
1804 struct ltdc_device *ldev = ddev->dev_private;
1811 regmap_read(ldev->regmap, LTDC_LCR, &lcr);
1813 ldev->caps.nb_layers = clamp((int)lcr, 1, LTDC_MAX_LAYER);
1816 regmap_read(ldev->regmap, LTDC_GC2R, &gc2r);
1818 ldev->caps.bus_width = 8 << bus_width_log2;
1819 regmap_read(ldev->regmap, LTDC_IDR, &ldev->caps.hw_version);
1821 switch (ldev->caps.hw_version) {
1824 ldev->caps.layer_ofs = LAY_OFS_0;
1825 ldev->caps.layer_regs = ltdc_layer_regs_a0;
1826 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a0;
1827 ldev->caps.pix_fmt_drm = ltdc_drm_fmt_a0;
1828 ldev->caps.pix_fmt_nb = ARRAY_SIZE(ltdc_drm_fmt_a0);
1829 ldev->caps.pix_fmt_flex = false;
1837 ldev->caps.non_alpha_only_l1 = true;
1838 ldev->caps.pad_max_freq_hz = 90000000;
1839 if (ldev->caps.hw_version == HWVER_10200)
1840 ldev->caps.pad_max_freq_hz = 65000000;
1841 ldev->caps.nb_irq = 2;
1842 ldev->caps.ycbcr_input = false;
1843 ldev->caps.ycbcr_output = false;
1844 ldev->caps.plane_reg_shadow = false;
1845 ldev->caps.crc = false;
1846 ldev->caps.dynamic_zorder = false;
1847 ldev->caps.plane_rotation = false;
1848 ldev->caps.fifo_threshold = false;
1851 ldev->caps.layer_ofs = LAY_OFS_0;
1852 ldev->caps.layer_regs = ltdc_layer_regs_a1;
1853 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a1;
1854 ldev->caps.pix_fmt_drm = ltdc_drm_fmt_a1;
1855 ldev->caps.pix_fmt_nb = ARRAY_SIZE(ltdc_drm_fmt_a1);
1856 ldev->caps.pix_fmt_flex = false;
1857 ldev->caps.non_alpha_only_l1 = false;
1858 ldev->caps.pad_max_freq_hz = 150000000;
1859 ldev->caps.nb_irq = 4;
1860 ldev->caps.ycbcr_input = false;
1861 ldev->caps.ycbcr_output = false;
1862 ldev->caps.plane_reg_shadow = false;
1863 ldev->caps.crc = false;
1864 ldev->caps.dynamic_zorder = false;
1865 ldev->caps.plane_rotation = false;
1866 ldev->caps.fifo_threshold = false;
1869 ldev->caps.layer_ofs = LAY_OFS_1;
1870 ldev->caps.layer_regs = ltdc_layer_regs_a2;
1871 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a2;
1872 ldev->caps.pix_fmt_drm = ltdc_drm_fmt_a2;
1873 ldev->caps.pix_fmt_nb = ARRAY_SIZE(ltdc_drm_fmt_a2);
1874 ldev->caps.pix_fmt_flex = true;
1875 ldev->caps.non_alpha_only_l1 = false;
1876 ldev->caps.pad_max_freq_hz = 90000000;
1877 ldev->caps.nb_irq = 2;
1878 ldev->caps.ycbcr_input = true;
1879 ldev->caps.ycbcr_output = true;
1880 ldev->caps.plane_reg_shadow = true;
1881 ldev->caps.crc = true;
1882 ldev->caps.dynamic_zorder = true;
1883 ldev->caps.plane_rotation = true;
1884 ldev->caps.fifo_threshold = true;
1895 struct ltdc_device *ldev = ddev->dev_private;
1898 clk_disable_unprepare(ldev->pixel_clk);
1903 struct ltdc_device *ldev = ddev->dev_private;
1908 ret = clk_prepare_enable(ldev->pixel_clk);
1920 struct ltdc_device *ldev = ddev->dev_private;
1938 ldev->pixel_clk = devm_clk_get(dev, "lcd");
1939 if (IS_ERR(ldev->pixel_clk)) {
1940 if (PTR_ERR(ldev->pixel_clk) != -EPROBE_DEFER)
1942 return PTR_ERR(ldev->pixel_clk);
1945 if (clk_prepare_enable(ldev->pixel_clk)) {
1986 mutex_init(&ldev->err_lock);
1995 ldev->regs = devm_ioremap_resource(dev, res);
1996 if (IS_ERR(ldev->regs)) {
1998 ret = PTR_ERR(ldev->regs);
2002 ldev->regmap = devm_regmap_init_mmio(&pdev->dev, ldev->regs, &stm32_ltdc_regmap_cfg);
2003 if (IS_ERR(ldev->regmap)) {
2005 ret = PTR_ERR(ldev->regmap);
2012 ldev->caps.hw_version);
2017 if (ldev->caps.fifo_threshold)
2018 regmap_clear_bits(ldev->regmap, LTDC_IER, IER_LIE | IER_RRIE | IER_FUWIE |
2021 regmap_clear_bits(ldev->regmap, LTDC_IER, IER_LIE | IER_RRIE | IER_FUWIE |
2024 DRM_DEBUG_DRIVER("ltdc hw version 0x%08x\n", ldev->caps.hw_version);
2027 ldev->transfer_err = 0;
2028 ldev->fifo_err = 0;
2029 ldev->fifo_warn = 0;
2030 ldev->fifo_threshold = FUT_DFT;
2032 for (i = 0; i < ldev->caps.nb_irq; i++) {
2067 clk_disable_unprepare(ldev->pixel_clk);
2078 clk_disable_unprepare(ldev->pixel_clk);