Lines Matching refs:ctx

136 dsi_reg_rd(struct dsi_context *ctx, u32 offset, u32 mask,
139 return (readl(ctx->base + offset) & mask) >> shift;
143 dsi_reg_wr(struct dsi_context *ctx, u32 offset, u32 mask,
148 ret = readl(ctx->base + offset);
151 writel(ret, ctx->base + offset);
155 dsi_reg_up(struct dsi_context *ctx, u32 offset, u32 mask,
158 u32 ret = readl(ctx->base + offset);
160 writel((ret & ~mask) | (val & mask), ctx->base + offset);
166 struct dsi_context *ctx = &dsi->ctx;
173 dsi_reg_up(ctx, PHY_TST_CTRL1, PHY_TESTEN, PHY_TESTEN);
174 dsi_reg_wr(ctx, PHY_TST_CTRL1, PHY_TESTDIN, 0, reg);
175 dsi_reg_up(ctx, PHY_TST_CTRL0, PHY_TESTCLK, PHY_TESTCLK);
176 dsi_reg_up(ctx, PHY_TST_CTRL0, PHY_TESTCLK, 0);
177 dsi_reg_up(ctx, PHY_TST_CTRL1, PHY_TESTEN, 0);
178 dsi_reg_wr(ctx, PHY_TST_CTRL1, PHY_TESTDIN, 0, val);
179 dsi_reg_up(ctx, PHY_TST_CTRL0, PHY_TESTCLK, PHY_TESTCLK);
180 dsi_reg_up(ctx, PHY_TST_CTRL0, PHY_TESTCLK, 0);
188 struct dsi_context *ctx = &dsi->ctx;
194 dsi_reg_up(ctx, PHY_TST_CTRL1, PHY_TESTEN, PHY_TESTEN);
195 dsi_reg_wr(ctx, PHY_TST_CTRL1, PHY_TESTDIN, 0, reg);
196 dsi_reg_up(ctx, PHY_TST_CTRL0, PHY_TESTCLK, PHY_TESTCLK);
197 dsi_reg_up(ctx, PHY_TST_CTRL0, PHY_TESTCLK, 0);
198 dsi_reg_up(ctx, PHY_TST_CTRL1, PHY_TESTEN, 0);
202 ret = dsi_reg_rd(ctx, PHY_TST_CTRL1, PHY_TESTDOUT, 8);
222 static int dphy_wait_pll_locked(struct dsi_context *ctx)
224 struct sprd_dsi *dsi = container_of(ctx, struct sprd_dsi, ctx);
228 if (dsi_reg_rd(ctx, PHY_STATUS, PHY_LOCK, 1))
237 static int dsi_wait_tx_payload_fifo_empty(struct dsi_context *ctx)
242 if (dsi_reg_rd(ctx, CMD_MODE_STATUS, GEN_CMD_WDATA_FIFO_EMPTY, 3))
250 static int dsi_wait_tx_cmd_fifo_empty(struct dsi_context *ctx)
255 if (dsi_reg_rd(ctx, CMD_MODE_STATUS, GEN_CMD_CMD_FIFO_EMPTY, 5))
263 static int dsi_wait_rd_resp_completed(struct dsi_context *ctx)
268 if (dsi_reg_rd(ctx, CMD_MODE_STATUS, GEN_CMD_RDCMD_DONE, 7))
389 static void sprd_dsi_init(struct dsi_context *ctx)
391 struct sprd_dsi *dsi = container_of(ctx, struct sprd_dsi, ctx);
397 writel(0, ctx->base + SOFT_RESET);
398 writel(0xffffffff, ctx->base + MASK_PROTOCOL_INT);
399 writel(0xffffffff, ctx->base + MASK_INTERNAL_INT);
400 writel(1, ctx->base + DSI_MODE_CFG);
401 dsi_reg_up(ctx, EOTP_EN, RX_EOTP_EN, 0);
402 dsi_reg_up(ctx, EOTP_EN, TX_EOTP_EN, 0);
403 dsi_reg_up(ctx, RX_PKT_CHECK_CONFIG, RX_PKT_ECC_EN, RX_PKT_ECC_EN);
404 dsi_reg_up(ctx, RX_PKT_CHECK_CONFIG, RX_PKT_CRC_EN, RX_PKT_CRC_EN);
405 writel(1, ctx->base + TA_EN);
406 dsi_reg_up(ctx, VIRTUAL_CHANNEL_ID, VIDEO_PKT_VCID, 0);
407 dsi_reg_up(ctx, VIRTUAL_CHANNEL_ID, GEN_RX_VCID, 0);
410 writel(div, ctx->base + TX_ESC_CLK_CONFIG);
412 max_rd_time = ns_to_cycle(ctx->max_rd_time, byte_clk);
413 writel(max_rd_time, ctx->base + MAX_READ_TIME);
415 data_hs2lp = ns_to_cycle(ctx->data_hs2lp, byte_clk);
416 data_lp2hs = ns_to_cycle(ctx->data_lp2hs, byte_clk);
417 clk_hs2lp = ns_to_cycle(ctx->clk_hs2lp, byte_clk);
418 clk_lp2hs = ns_to_cycle(ctx->clk_lp2hs, byte_clk);
419 dsi_reg_wr(ctx, PHY_DATALANE_TIME_CONFIG,
421 dsi_reg_wr(ctx, PHY_DATALANE_TIME_CONFIG,
423 dsi_reg_wr(ctx, PHY_CLKLANE_TIME_CONFIG,
425 dsi_reg_wr(ctx, PHY_CLKLANE_TIME_CONFIG,
428 writel(1, ctx->base + SOFT_RESET);
434 static void sprd_dsi_fini(struct dsi_context *ctx)
436 writel(0xffffffff, ctx->base + MASK_PROTOCOL_INT);
437 writel(0xffffffff, ctx->base + MASK_INTERNAL_INT);
438 writel(0, ctx->base + SOFT_RESET);
447 static int sprd_dsi_dpi_video(struct dsi_context *ctx)
449 struct sprd_dsi *dsi = container_of(ctx, struct sprd_dsi, ctx);
450 struct videomode *vm = &ctx->vm;
477 writel(0, ctx->base + SOFT_RESET);
478 dsi_reg_wr(ctx, VID_MODE_CFG, FRAME_BTA_ACK_EN, 15, ctx->frame_ack_en);
479 dsi_reg_wr(ctx, DPI_VIDEO_FORMAT, DPI_VIDEO_MODE_FORMAT, 0, coding);
480 dsi_reg_wr(ctx, VID_MODE_CFG, VID_MODE_TYPE, 0, ctx->burst_mode);
482 dsi_reg_wr(ctx, VIDEO_SIG_DELAY_CONFIG, VIDEO_SIG_DELAY, 0, byte_cycle);
484 writel(byte_cycle, ctx->base + VIDEO_LINE_TIME);
486 dsi_reg_wr(ctx, VIDEO_LINE_HBLK_TIME, VIDEO_LINE_HSA_TIME, 16, byte_cycle);
488 dsi_reg_wr(ctx, VIDEO_LINE_HBLK_TIME, VIDEO_LINE_HBP_TIME, 0, byte_cycle);
489 writel(vm->vactive, ctx->base + VIDEO_VACTIVE_LINES);
490 dsi_reg_wr(ctx, VIDEO_VBLK_LINES, VFP_LINES, 0, vm->vfront_porch);
491 dsi_reg_wr(ctx, VIDEO_VBLK_LINES, VBP_LINES, 10, vm->vback_porch);
492 dsi_reg_wr(ctx, VIDEO_VBLK_LINES, VSA_LINES, 20, vm->vsync_len);
493 dsi_reg_up(ctx, VID_MODE_CFG, LP_HBP_EN | LP_HFP_EN | LP_VACT_EN |
500 writel(div, ctx->base + TIMEOUT_CNT_CLK_CONFIG);
501 writel(hs_to / div, ctx->base + LRX_H_TO_CONFIG);
502 writel(hs_to / div, ctx->base + HTX_TO_CONFIG);
507 if (ctx->burst_mode == VIDEO_BURST_WITH_SYNC_PULSES) {
508 dsi_reg_wr(ctx, VIDEO_PKT_CONFIG, VIDEO_PKT_SIZE, 0, video_size);
509 writel(0, ctx->base + VIDEO_NULLPKT_SIZE);
510 dsi_reg_up(ctx, VIDEO_PKT_CONFIG, VIDEO_LINE_CHUNK_NUM, 0);
569 dsi_reg_wr(ctx, VIDEO_PKT_CONFIG, VIDEO_PKT_SIZE, 0, video_size);
570 writel(null_pkt_size, ctx->base + VIDEO_NULLPKT_SIZE);
571 dsi_reg_wr(ctx, VIDEO_PKT_CONFIG, VIDEO_LINE_CHUNK_NUM, 16, chunks);
574 writel(ctx->int0_mask, ctx->base + MASK_PROTOCOL_INT);
575 writel(ctx->int1_mask, ctx->base + MASK_INTERNAL_INT);
576 writel(1, ctx->base + SOFT_RESET);
581 static void sprd_dsi_edpi_video(struct dsi_context *ctx)
583 struct sprd_dsi *dsi = container_of(ctx, struct sprd_dsi, ctx);
586 u32 hactive = ctx->vm.hactive;
595 writel(0, ctx->base + SOFT_RESET);
596 dsi_reg_wr(ctx, DPI_VIDEO_FORMAT, DPI_VIDEO_MODE_FORMAT, 0, coding);
597 dsi_reg_wr(ctx, CMD_MODE_CFG, TEAR_FX_EN, 0, ctx->te_ack_en);
600 writel(hactive, ctx->base + DCS_WM_PKT_SIZE);
602 writel(max_fifo_len, ctx->base + DCS_WM_PKT_SIZE);
604 writel(ctx->int0_mask, ctx->base + MASK_PROTOCOL_INT);
605 writel(ctx->int1_mask, ctx->base + MASK_INTERNAL_INT);
606 writel(1, ctx->base + SOFT_RESET);
619 static int sprd_dsi_wr_pkt(struct dsi_context *ctx, u8 vc, u8 type,
622 struct sprd_dsi *dsi = container_of(ctx, struct sprd_dsi, ctx);
631 ret = dsi_wait_tx_payload_fifo_empty(ctx);
643 writel(payload, ctx->base + GEN_PLD_DATA);
653 ret = dsi_wait_tx_cmd_fifo_empty(ctx);
660 ctx->base + GEN_HDR);
674 static int sprd_dsi_rd_pkt(struct dsi_context *ctx, u8 vc, u8 type,
678 struct sprd_dsi *dsi = container_of(ctx, struct sprd_dsi, ctx);
687 ret = dsi_reg_rd(ctx, CMD_MODE_STATUS, GEN_CMD_CMD_FIFO_EMPTY, 5);
692 ctx->base + GEN_HDR);
695 ret = dsi_wait_rd_resp_completed(ctx);
702 ret = dsi_reg_rd(ctx, CMD_MODE_STATUS, GEN_CMD_RDATA_FIFO_EMPTY, 1);
709 temp = readl(ctx->base + GEN_PLD_DATA);
720 ret = dsi_reg_rd(ctx, CMD_MODE_STATUS, GEN_CMD_RDATA_FIFO_EMPTY, 1);
728 static void sprd_dsi_set_work_mode(struct dsi_context *ctx, u8 mode)
731 writel(1, ctx->base + DSI_MODE_CFG);
733 writel(0, ctx->base + DSI_MODE_CFG);
736 static void sprd_dsi_state_reset(struct dsi_context *ctx)
738 writel(0, ctx->base + SOFT_RESET);
740 writel(1, ctx->base + SOFT_RESET);
743 static int sprd_dphy_init(struct dsi_context *ctx)
745 struct sprd_dsi *dsi = container_of(ctx, struct sprd_dsi, ctx);
748 dsi_reg_up(ctx, PHY_INTERFACE_CTRL, RF_PHY_RESET_N, 0);
749 dsi_reg_up(ctx, PHY_INTERFACE_CTRL, RF_PHY_SHUTDOWN, 0);
750 dsi_reg_up(ctx, PHY_INTERFACE_CTRL, RF_PHY_CLK_EN, 0);
752 dsi_reg_up(ctx, PHY_TST_CTRL0, PHY_TESTCLR, 0);
753 dsi_reg_up(ctx, PHY_TST_CTRL0, PHY_TESTCLR, PHY_TESTCLR);
754 dsi_reg_up(ctx, PHY_TST_CTRL0, PHY_TESTCLR, 0);
756 dphy_pll_config(ctx);
757 dphy_timing_config(ctx);
759 dsi_reg_up(ctx, PHY_INTERFACE_CTRL, RF_PHY_SHUTDOWN, RF_PHY_SHUTDOWN);
760 dsi_reg_up(ctx, PHY_INTERFACE_CTRL, RF_PHY_RESET_N, RF_PHY_RESET_N);
761 writel(0x1C, ctx->base + PHY_MIN_STOP_TIME);
762 dsi_reg_up(ctx, PHY_INTERFACE_CTRL, RF_PHY_CLK_EN, RF_PHY_CLK_EN);
763 writel(dsi->slave->lanes - 1, ctx->base + PHY_LANE_NUM_CONFIG);
765 ret = dphy_wait_pll_locked(ctx);
774 static void sprd_dphy_fini(struct dsi_context *ctx)
776 dsi_reg_up(ctx, PHY_INTERFACE_CTRL, RF_PHY_RESET_N, 0);
777 dsi_reg_up(ctx, PHY_INTERFACE_CTRL, RF_PHY_SHUTDOWN, 0);
778 dsi_reg_up(ctx, PHY_INTERFACE_CTRL, RF_PHY_RESET_N, RF_PHY_RESET_N);
787 drm_display_mode_to_videomode(adj_mode, &dsi->ctx.vm);
794 struct dsi_context *ctx = &dsi->ctx;
796 if (ctx->enabled) {
801 sprd_dsi_init(ctx);
802 if (ctx->work_mode == DSI_MODE_VIDEO)
803 sprd_dsi_dpi_video(ctx);
805 sprd_dsi_edpi_video(ctx);
807 sprd_dphy_init(ctx);
809 sprd_dsi_set_work_mode(ctx, ctx->work_mode);
810 sprd_dsi_state_reset(ctx);
813 dsi_reg_up(ctx, PHY_CLK_LANE_LP_CTRL, AUTO_CLKLANE_CTRL_EN,
816 dsi_reg_up(ctx, PHY_CLK_LANE_LP_CTRL, RF_PHY_CLK_EN, RF_PHY_CLK_EN);
817 dsi_reg_up(ctx, PHY_CLK_LANE_LP_CTRL, PHY_CLKLANE_TX_REQ_HS,
819 dphy_wait_pll_locked(ctx);
824 ctx->enabled = true;
831 struct dsi_context *ctx = &dsi->ctx;
833 if (!ctx->enabled) {
839 sprd_dphy_fini(ctx);
840 sprd_dsi_fini(ctx);
842 ctx->enabled = false;
903 struct dsi_context *ctx = &dsi->ctx;
912 ctx->base = devm_ioremap(dev, res->start, resource_size(res));
913 if (!ctx->base) {
918 ctx->regmap = devm_regmap_init(dev, &regmap_tst_io, dsi, &byte_config);
919 if (IS_ERR(ctx->regmap)) {
921 return PTR_ERR(ctx->regmap);
924 ctx->data_hs2lp = 120;
925 ctx->data_lp2hs = 500;
926 ctx->clk_hs2lp = 4;
927 ctx->clk_lp2hs = 15;
928 ctx->max_rd_time = 6000;
929 ctx->int0_mask = 0xffffffff;
930 ctx->int1_mask = 0xffffffff;
931 ctx->enabled = true;
978 struct dsi_context *ctx = &dsi->ctx;
983 ctx->work_mode = DSI_MODE_VIDEO;
985 ctx->work_mode = DSI_MODE_CMD;
988 ctx->burst_mode = VIDEO_BURST_WITH_SYNC_PULSES;
990 ctx->burst_mode = VIDEO_NON_BURST_WITH_SYNC_PULSES;
992 ctx->burst_mode = VIDEO_NON_BURST_WITH_SYNC_EVENTS;
1015 return sprd_dsi_rd_pkt(&dsi->ctx, msg->channel, msg->type,
1020 return sprd_dsi_wr_pkt(&dsi->ctx, msg->channel, msg->type,