Lines Matching refs:dsi
359 static inline void dsi_write(struct dw_mipi_dsi_rockchip *dsi, u32 reg, u32 val)
361 writel(val, dsi->base + reg);
364 static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi_rockchip *dsi,
373 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
375 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) |
378 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR);
380 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) |
383 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
389 static inline unsigned int ns2bc(struct dw_mipi_dsi_rockchip *dsi, int ns)
391 return DIV_ROUND_UP(ns * dsi->lane_mbps / 8, 1000);
397 static inline unsigned int ns2ui(struct dw_mipi_dsi_rockchip *dsi, int ns)
399 return DIV_ROUND_UP(ns * dsi->lane_mbps, 1000);
404 struct dw_mipi_dsi_rockchip *dsi = priv_data;
407 if (dsi->phy)
422 vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200;
424 i = max_mbps_to_parameter(dsi->lane_mbps);
426 DRM_DEV_ERROR(dsi->dev,
428 dsi->lane_mbps);
432 ret = clk_prepare_enable(dsi->phy_cfg_clk);
434 DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk\n");
438 dw_mipi_dsi_phy_write(dsi, PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL,
444 dw_mipi_dsi_phy_write(dsi, PLL_CP_CONTROL_PLL_LOCK_BYPASS,
446 dw_mipi_dsi_phy_write(dsi, PLL_LPF_AND_CP_CONTROL,
450 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_0,
453 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_DIVIDER_RATIO,
454 INPUT_DIVIDER(dsi->input_div));
455 dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO,
456 LOOP_DIV_LOW_SEL(dsi->feedback_div) |
464 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL,
466 dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO,
467 LOOP_DIV_HIGH_SEL(dsi->feedback_div) |
469 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL,
472 dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY,
474 dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY,
477 dw_mipi_dsi_phy_write(dsi, BANDGAP_AND_BIAS_CONTROL,
481 dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL,
484 dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL,
489 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL,
490 TLP_PROGRAM_EN | ns2bc(dsi, 500));
491 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL,
492 THS_PRE_PROGRAM_EN | ns2ui(dsi, 40));
493 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL,
494 THS_ZERO_PROGRAM_EN | ns2bc(dsi, 300));
495 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL,
496 THS_PRE_PROGRAM_EN | ns2ui(dsi, 100));
497 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL,
498 BIT(5) | ns2bc(dsi, 100));
499 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_POST_TIME_CONTROL,
500 BIT(5) | (ns2bc(dsi, 60) + 7));
502 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL,
503 TLP_PROGRAM_EN | ns2bc(dsi, 500));
504 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL,
505 THS_PRE_PROGRAM_EN | (ns2ui(dsi, 50) + 20));
506 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL,
507 THS_ZERO_PROGRAM_EN | (ns2bc(dsi, 140) + 2));
508 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL,
509 THS_PRE_PROGRAM_EN | (ns2ui(dsi, 60) + 8));
510 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL,
511 BIT(5) | ns2bc(dsi, 100));
513 clk_disable_unprepare(dsi->phy_cfg_clk);
520 struct dw_mipi_dsi_rockchip *dsi = priv_data;
523 ret = phy_set_mode(dsi->phy, PHY_MODE_MIPI_DPHY);
525 DRM_DEV_ERROR(dsi->dev, "failed to set phy mode: %d\n", ret);
529 phy_configure(dsi->phy, &dsi->phy_opts);
530 phy_power_on(dsi->phy);
535 struct dw_mipi_dsi_rockchip *dsi = priv_data;
537 phy_power_off(dsi->phy);
545 struct dw_mipi_dsi_rockchip *dsi = priv_data;
557 dsi->format = format;
558 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
560 DRM_DEV_ERROR(dsi->dev,
562 dsi->format);
573 DRM_DEV_ERROR(dsi->dev,
578 if (dsi->phy) {
581 &dsi->phy_opts.mipi_dphy);
582 dsi->lane_mbps = target_mbps;
583 *lane_mbps = dsi->lane_mbps;
588 fin = clk_get_rate(dsi->pllref_clk);
631 dsi->lane_mbps = DIV_ROUND_UP(best_freq, USEC_PER_SEC);
632 *lane_mbps = dsi->lane_mbps;
633 dsi->input_div = best_prediv;
634 dsi->feedback_div = best_fbdiv;
636 DRM_DEV_ERROR(dsi->dev, "Can not find best_freq for DPHY\n");
728 static void dw_mipi_dsi_rockchip_config(struct dw_mipi_dsi_rockchip *dsi)
730 if (dsi->cdata->lanecfg1_grf_reg)
731 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg1_grf_reg,
732 dsi->cdata->lanecfg1);
734 if (dsi->cdata->lanecfg2_grf_reg)
735 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg2_grf_reg,
736 dsi->cdata->lanecfg2);
738 if (dsi->cdata->enable_grf_reg)
739 regmap_write(dsi->grf_regmap, dsi->cdata->enable_grf_reg,
740 dsi->cdata->enable);
743 static void dw_mipi_dsi_rockchip_set_lcdsel(struct dw_mipi_dsi_rockchip *dsi,
746 if (dsi->cdata->lcdsel_grf_reg)
747 regmap_write(dsi->grf_regmap, dsi->cdata->lcdsel_grf_reg,
748 mux ? dsi->cdata->lcdsel_lit : dsi->cdata->lcdsel_big);
757 struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder);
759 switch (dsi->format) {
775 if (dsi->slave)
783 struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder);
786 mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node,
787 &dsi->encoder.encoder);
796 ret = clk_prepare_enable(dsi->grf_clk);
798 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret);
802 dw_mipi_dsi_rockchip_set_lcdsel(dsi, mux);
803 if (dsi->slave)
804 dw_mipi_dsi_rockchip_set_lcdsel(dsi->slave, mux);
806 clk_disable_unprepare(dsi->grf_clk);
815 static int rockchip_dsi_drm_create_encoder(struct dw_mipi_dsi_rockchip *dsi,
818 struct drm_encoder *encoder = &dsi->encoder.encoder;
822 dsi->dev->of_node);
836 *dw_mipi_dsi_rockchip_find_second(struct dw_mipi_dsi_rockchip *dsi)
841 match = of_match_device(dsi->dev->driver->of_match_table, dsi->dev);
843 local = of_graph_get_remote_node(dsi->dev->of_node, 1, 0);
852 if (node == dsi->dev->of_node)
899 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev);
905 second = dw_mipi_dsi_rockchip_find_second(dsi);
910 master1 = of_property_read_bool(dsi->dev->of_node,
916 DRM_DEV_ERROR(dsi->dev, "only one clock-master allowed\n");
921 DRM_DEV_ERROR(dsi->dev, "no clock-master defined\n");
927 dsi->is_slave = true;
931 dsi->slave = dev_get_drvdata(second);
932 if (!dsi->slave) {
937 dsi->slave->is_slave = true;
938 dw_mipi_dsi_set_slave(dsi->dmd, dsi->slave->dmd);
942 pm_runtime_get_sync(dsi->dev);
943 if (dsi->slave)
944 pm_runtime_get_sync(dsi->slave->dev);
946 ret = clk_prepare_enable(dsi->pllref_clk);
958 ret = clk_prepare_enable(dsi->grf_clk);
960 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret);
964 dw_mipi_dsi_rockchip_config(dsi);
965 if (dsi->slave)
966 dw_mipi_dsi_rockchip_config(dsi->slave);
968 clk_disable_unprepare(dsi->grf_clk);
970 ret = rockchip_dsi_drm_create_encoder(dsi, drm_dev);
975 rockchip_drm_encoder_set_crtc_endpoint_id(&dsi->encoder,
978 ret = dw_mipi_dsi_bind(dsi->dmd, &dsi->encoder.encoder);
984 dsi->dsi_bound = true;
989 clk_disable_unprepare(dsi->pllref_clk);
991 pm_runtime_put(dsi->dev);
992 if (dsi->slave)
993 pm_runtime_put(dsi->slave->dev);
1002 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev);
1004 if (dsi->is_slave)
1007 dsi->dsi_bound = false;
1009 dw_mipi_dsi_unbind(dsi->dmd);
1011 clk_disable_unprepare(dsi->pllref_clk);
1013 pm_runtime_put(dsi->dev);
1014 if (dsi->slave)
1015 pm_runtime_put(dsi->slave->dev);
1026 struct dw_mipi_dsi_rockchip *dsi = priv_data;
1030 mutex_lock(&dsi->usage_mutex);
1032 if (dsi->usage_mode != DW_DSI_USAGE_IDLE) {
1033 DRM_DEV_ERROR(dsi->dev, "dsi controller already in use\n");
1034 mutex_unlock(&dsi->usage_mutex);
1038 dsi->usage_mode = DW_DSI_USAGE_DSI;
1039 mutex_unlock(&dsi->usage_mutex);
1041 ret = component_add(dsi->dev, &dw_mipi_dsi_rockchip_ops);
1043 DRM_DEV_ERROR(dsi->dev, "Failed to register component: %d\n",
1048 second = dw_mipi_dsi_rockchip_find_second(dsi);
1066 mutex_lock(&dsi->usage_mutex);
1067 dsi->usage_mode = DW_DSI_USAGE_IDLE;
1068 mutex_unlock(&dsi->usage_mutex);
1075 struct dw_mipi_dsi_rockchip *dsi = priv_data;
1078 second = dw_mipi_dsi_rockchip_find_second(dsi);
1082 component_del(dsi->dev, &dw_mipi_dsi_rockchip_ops);
1084 mutex_lock(&dsi->usage_mutex);
1085 dsi->usage_mode = DW_DSI_USAGE_IDLE;
1086 mutex_unlock(&dsi->usage_mutex);
1123 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy);
1126 mutex_lock(&dsi->usage_mutex);
1128 if (dsi->usage_mode != DW_DSI_USAGE_IDLE) {
1129 DRM_DEV_ERROR(dsi->dev, "dsi controller already in use\n");
1130 mutex_unlock(&dsi->usage_mutex);
1134 dsi->usage_mode = DW_DSI_USAGE_PHY;
1135 mutex_unlock(&dsi->usage_mutex);
1137 ret = component_add(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops);
1141 if (dsi->cdata->dphy_rx_init) {
1142 ret = clk_prepare_enable(dsi->pclk);
1146 ret = clk_prepare_enable(dsi->grf_clk);
1148 clk_disable_unprepare(dsi->pclk);
1152 ret = dsi->cdata->dphy_rx_init(phy);
1153 clk_disable_unprepare(dsi->grf_clk);
1154 clk_disable_unprepare(dsi->pclk);
1162 component_del(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops);
1164 mutex_lock(&dsi->usage_mutex);
1165 dsi->usage_mode = DW_DSI_USAGE_IDLE;
1166 mutex_unlock(&dsi->usage_mutex);
1173 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy);
1175 component_del(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops);
1177 mutex_lock(&dsi->usage_mutex);
1178 dsi->usage_mode = DW_DSI_USAGE_IDLE;
1179 mutex_unlock(&dsi->usage_mutex);
1187 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy);
1194 dsi->dphy_config = *config;
1195 dsi->lane_mbps = div_u64(config->hs_clk_rate, 1000 * 1000 * 1);
1202 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy);
1205 DRM_DEV_DEBUG(dsi->dev, "lanes %d - data_rate_mbps %u\n",
1206 dsi->dphy_config.lanes, dsi->lane_mbps);
1208 i = max_mbps_to_parameter(dsi->lane_mbps);
1210 DRM_DEV_ERROR(dsi->dev, "failed to get parameter for %dmbps clock\n",
1211 dsi->lane_mbps);
1215 ret = pm_runtime_resume_and_get(dsi->dev);
1217 DRM_DEV_ERROR(dsi->dev, "failed to enable device: %d\n", ret);
1221 ret = clk_prepare_enable(dsi->pclk);
1223 DRM_DEV_ERROR(dsi->dev, "Failed to enable pclk: %d\n", ret);
1227 ret = clk_prepare_enable(dsi->grf_clk);
1229 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret);
1233 ret = clk_prepare_enable(dsi->phy_cfg_clk);
1235 DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk: %d\n", ret);
1240 if (dsi->cdata->dphy_rx_power_on) {
1241 ret = dsi->cdata->dphy_rx_power_on(phy);
1243 DRM_DEV_ERROR(dsi->dev, "hardware-specific phy bringup failed: %d\n", ret);
1252 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_CLK, 0);
1253 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_0,
1255 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_1, 0);
1256 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_2, 0);
1257 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_3, 0);
1260 dw_mipi_dsi_phy_write(dsi, 0x0, 0);
1262 clk_disable_unprepare(dsi->phy_cfg_clk);
1263 clk_disable_unprepare(dsi->grf_clk);
1268 clk_disable_unprepare(dsi->phy_cfg_clk);
1270 clk_disable_unprepare(dsi->grf_clk);
1272 clk_disable_unprepare(dsi->pclk);
1274 pm_runtime_put(dsi->dev);
1280 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy);
1283 ret = clk_prepare_enable(dsi->grf_clk);
1285 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret);
1289 if (dsi->cdata->dphy_rx_power_off) {
1290 ret = dsi->cdata->dphy_rx_power_off(phy);
1292 DRM_DEV_ERROR(dsi->dev, "hardware-specific phy shutdown failed: %d\n", ret);
1295 clk_disable_unprepare(dsi->grf_clk);
1296 clk_disable_unprepare(dsi->pclk);
1298 pm_runtime_put(dsi->dev);
1313 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev);
1320 if (dsi->dsi_bound) {
1321 ret = clk_prepare_enable(dsi->grf_clk);
1323 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret);
1327 dw_mipi_dsi_rockchip_config(dsi);
1328 if (dsi->slave)
1329 dw_mipi_dsi_rockchip_config(dsi->slave);
1331 clk_disable_unprepare(dsi->grf_clk);
1345 struct dw_mipi_dsi_rockchip *dsi;
1352 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1353 if (!dsi)
1357 dsi->base = devm_ioremap_resource(dev, res);
1358 if (IS_ERR(dsi->base)) {
1359 DRM_DEV_ERROR(dev, "Unable to get dsi registers\n");
1360 return PTR_ERR(dsi->base);
1366 dsi->cdata = &cdata[i];
1373 if (!dsi->cdata) {
1374 DRM_DEV_ERROR(dev, "no dsi-config for %s node\n", np->name);
1379 dsi->phy = devm_phy_optional_get(dev, "dphy");
1380 if (IS_ERR(dsi->phy)) {
1381 ret = PTR_ERR(dsi->phy);
1386 dsi->pclk = devm_clk_get(dev, "pclk");
1387 if (IS_ERR(dsi->pclk)) {
1388 ret = PTR_ERR(dsi->pclk);
1393 dsi->pllref_clk = devm_clk_get(dev, "ref");
1394 if (IS_ERR(dsi->pllref_clk)) {
1395 if (dsi->phy) {
1400 dsi->pllref_clk = NULL;
1402 ret = PTR_ERR(dsi->pllref_clk);
1410 if (dsi->cdata->flags & DW_MIPI_NEEDS_PHY_CFG_CLK) {
1411 dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg");
1412 if (IS_ERR(dsi->phy_cfg_clk)) {
1413 ret = PTR_ERR(dsi->phy_cfg_clk);
1420 if (dsi->cdata->flags & DW_MIPI_NEEDS_GRF_CLK) {
1421 dsi->grf_clk = devm_clk_get(dev, "grf");
1422 if (IS_ERR(dsi->grf_clk)) {
1423 ret = PTR_ERR(dsi->grf_clk);
1429 dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1430 if (IS_ERR(dsi->grf_regmap)) {
1432 return PTR_ERR(dsi->grf_regmap);
1435 dsi->dev = dev;
1436 dsi->pdata.base = dsi->base;
1437 dsi->pdata.max_data_lanes = dsi->cdata->max_data_lanes;
1438 dsi->pdata.phy_ops = &dw_mipi_dsi_rockchip_phy_ops;
1439 dsi->pdata.host_ops = &dw_mipi_dsi_rockchip_host_ops;
1440 dsi->pdata.priv_data = dsi;
1441 platform_set_drvdata(pdev, dsi);
1443 mutex_init(&dsi->usage_mutex);
1445 dsi->dphy = devm_phy_create(dev, NULL, &dw_mipi_dsi_dphy_ops);
1446 if (IS_ERR(dsi->dphy)) {
1448 return PTR_ERR(dsi->dphy);
1451 phy_set_drvdata(dsi->dphy, dsi);
1456 dsi->dmd = dw_mipi_dsi_probe(pdev, &dsi->pdata);
1457 if (IS_ERR(dsi->dmd)) {
1458 ret = PTR_ERR(dsi->dmd);
1470 struct dw_mipi_dsi_rockchip *dsi = platform_get_drvdata(pdev);
1472 dw_mipi_dsi_remove(dsi->dmd);
1515 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy);
1521 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24,
1523 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24,
1525 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24,
1527 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23,
1535 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy);
1538 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_TESTCLR);
1541 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24,
1543 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24,
1546 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23,
1548 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23,
1552 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24,
1554 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23,
1559 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
1563 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23,
1564 HIWORD_UPDATE(GENMASK(dsi->dphy_config.lanes - 1, 0),
1574 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy);
1576 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23,
1656 .compatible = "rockchip,px30-mipi-dsi",
1659 .compatible = "rockchip,rk3288-mipi-dsi",
1662 .compatible = "rockchip,rk3399-mipi-dsi",
1665 .compatible = "rockchip,rk3568-mipi-dsi",
1678 .name = "dw-mipi-dsi-rockchip",