Lines Matching refs:value
322 u32 value;
334 value = RREG32_SMC(GFX_POWER_GATING_CNTL);
335 value &= ~(SSSD_MASK | PDS_DIV_MASK);
337 value |= SSSD(1);
338 value |= PDS_DIV(dividers.post_div);
339 WREG32_SMC(GFX_POWER_GATING_CNTL, value);
475 u32 value;
478 value = RREG32_SMC(PM_I_CNTL_1);
479 value &= ~DS_PG_CNTL_MASK;
480 value |= DS_PG_CNTL(1);
481 WREG32_SMC(PM_I_CNTL_1, value);
483 value = RREG32_SMC(SMU_S_PG_CNTL);
484 value &= ~DS_PG_EN_MASK;
485 value |= DS_PG_EN(1);
486 WREG32_SMC(SMU_S_PG_CNTL, value);
488 value = RREG32_SMC(SMU_S_PG_CNTL);
489 value &= ~DS_PG_EN_MASK;
490 WREG32_SMC(SMU_S_PG_CNTL, value);
492 value = RREG32_SMC(PM_I_CNTL_1);
493 value &= ~DS_PG_CNTL_MASK;
494 WREG32_SMC(PM_I_CNTL_1, value);
544 u32 value;
552 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix);
553 value &= ~CLK_DIVIDER_MASK;
554 value |= CLK_DIVIDER(dividers.post_div);
555 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value);
562 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_PG_CNTL + ix);
563 value &= ~PD_SCLK_DIVIDER_MASK;
564 value |= PD_SCLK_DIVIDER(dividers.post_div);
565 WREG32_SMC(SMU_SCLK_DPM_STATE_0_PG_CNTL + ix, value);
571 u32 value;
574 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix);
575 value &= ~DS_DIV_MASK;
576 value |= DS_DIV(divider);
577 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value);
583 u32 value;
586 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix);
587 value &= ~DS_SH_DIV_MASK;
588 value |= DS_SH_DIV(divider);
589 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value);
596 u32 value;
599 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix);
600 value &= ~VID_MASK;
601 value |= VID(vid_7bit);
602 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value);
604 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix);
605 value &= ~LVRT_MASK;
606 value |= LVRT(0);
607 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value);
613 u32 value;
616 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_3 + ix);
617 value &= ~GNB_SLOW_MASK;
618 value |= GNB_SLOW(gnb_slow);
619 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_3 + ix, value);
625 u32 value;
628 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_3 + ix);
629 value &= ~FORCE_NBPS1_MASK;
630 value |= FORCE_NBPS1(force_nbp_state);
631 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_3 + ix, value);
637 u32 value;
640 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix);
641 value &= ~DISPLAY_WM_MASK;
642 value |= DISPLAY_WM(wm);
643 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value);
649 u32 value;
652 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix);
653 value &= ~VCE_WM_MASK;
654 value |= VCE_WM(wm);
655 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value);
661 u32 value;
664 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_AT + ix);
665 value &= ~AT_MASK;
666 value |= AT(at);
667 WREG32_SMC(SMU_SCLK_DPM_STATE_0_AT + ix, value);
692 u32 value;
695 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix);
696 value &= ~STATE_VALID_MASK;
698 value |= STATE_VALID(1);
699 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value);
712 u32 value = RREG32_SMC(SMU_SCLK_DPM_CNTL);
714 value &= ~(SCLK_DPM_EN_MASK | SCLK_DPM_BOOT_STATE_MASK | VOLTAGE_CHG_EN_MASK);
715 value |= SCLK_DPM_EN(1) | SCLK_DPM_BOOT_STATE(0) | VOLTAGE_CHG_EN(1);
716 WREG32_SMC(SMU_SCLK_DPM_CNTL, value);
964 u32 value = RREG32_SMC(SMU_SCLK_DPM_TTT);
966 value &= ~(HT_MASK | LT_MASK);
967 value |= HT((pi->thermal_auto_throttling + 49) * 8);
968 value |= LT((pi->thermal_auto_throttling + 49 - pi->sys_info.htc_hyst_lmt) * 8);
969 WREG32_SMC(SMU_SCLK_DPM_TTT, value);
974 u32 value = RREG32_SMC(SMU_SCLK_DPM_TT_CNTL);
976 value &= ~SCLK_TT_EN_MASK;
977 value |= SCLK_TT_EN(1);
978 WREG32_SMC(SMU_SCLK_DPM_TT_CNTL, value);
987 u32 value;
993 value = RREG32_SMC(PM_I_CNTL_1);
994 value &= ~SCLK_DPM_MASK;
995 value |= SCLK_DPM(ni);
996 WREG32_SMC(PM_I_CNTL_1, value);