Lines Matching refs:vddc
1753 s64 kt, kv, leakage_w, i_leakage, vddc;
1758 vddc = div64_s64(drm_int2fixp(v), 1000);
1767 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept;
1770 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc)));
1772 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1791 s64 kt, kv, leakage_w, i_leakage, vddc;
1794 vddc = div64_s64(drm_int2fixp(v), 1000);
1798 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc)));
1800 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
2273 SISLANDS_SMC_VOLTAGE_VALUE vddc;
2330 state->performance_levels[i-1].vddc, &vddc);
2334 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc);
2339 state->performance_levels[i].vddc, &vddc);
2343 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc);
2529 if (table->entries[i].vddc > *max)
2530 *max = table->entries[i].vddc;
2531 if (table->entries[i].vddc < *min)
2532 *min = table->entries[i].vddc;
2954 u16 vddc, vddci, min_vce_voltage = 0;
3012 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc)
3013 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc;
3021 if (ps->performance_levels[i].vddc > max_limits->vddc)
3022 ps->performance_levels[i].vddc = max_limits->vddc;
3071 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc;
3074 vddc = ps->performance_levels[0].vddc;
3087 ps->performance_levels[0].vddc = vddc;
3098 ps->performance_levels[i].vddc = vddc;
3104 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
3105 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
3133 if (ps->performance_levels[i].vddc < min_vce_voltage)
3134 ps->performance_levels[i].vddc = min_vce_voltage;
3137 max_limits->vddc, &ps->performance_levels[i].vddc);
3143 max_limits->vddc, &ps->performance_levels[i].vddc);
3146 max_limits->vddc, &ps->performance_levels[i].vddc);
3151 max_limits->vddc, max_limits->vddci,
3152 &ps->performance_levels[i].vddc,
3158 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
3216 u16 vddc, count = 0;
3220 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i);
3222 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) {
3223 si_pi->leakage_voltage.entries[count].voltage = vddc;
4146 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4149 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4161 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4164 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4171 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
4400 initial_state->performance_levels[0].vddc,
4401 &table->initialState.level.vddc);
4407 &table->initialState.level.vddc,
4411 table->initialState.level.vddc.index,
4424 initial_state->performance_levels[0].vddc,
4427 &table->initialState.level.vddc);
4494 pi->acpi_vddc, &table->ACPIState.level.vddc);
4499 &table->ACPIState.level.vddc, &std_vddc);
4502 table->ACPIState.level.vddc.index,
4513 &table->ACPIState.level.vddc);
4517 pi->min_vddc_in_table, &table->ACPIState.level.vddc);
4522 &table->ACPIState.level.vddc, &std_vddc);
4526 table->ACPIState.level.vddc.index,
4540 &table->ACPIState.level.vddc);
4631 state->level.std_vddc = state->level.vddc;
4740 if (ulv->supported && ulv->pl.vddc) {
5028 pl->vddc, &level->vddc);
5033 ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc);
5038 level->vddc.index, &level->std_vddc);
5052 pl->vddc,
5055 &level->vddc);
5144 if (ulv->pl.vddc <
5280 if (ulv->supported && ulv->pl.vddc) {
5653 if (ulv->supported && ulv->pl.vddc != 0)
6731 pl->vddc = le16_to_cpu(clock_info->si.usVDDC);
6739 /* patch up vddc if necessary */
6740 ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc,
6743 pl->vddc = leakage_voltage;
6746 pi->acpi_vddc = pl->vddc;
6762 if (pi->min_vddc_in_table > pl->vddc)
6763 pi->min_vddc_in_table = pl->vddc;
6765 if (pi->max_vddc_in_table < pl->vddc)
6766 pi->max_vddc_in_table = pl->vddc;
6770 u16 vddc, vddci, mvdd;
6771 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
6774 pl->vddc = vddc;
6783 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
7088 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
7089 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);