Lines Matching defs:ulv
4614 struct si_ulv_param *ulv = &si_pi->ulv;
4618 ret = si_convert_power_level_to_smc(rdev, &ulv->pl,
4627 if (ulv->one_pcie_lane_in_ulv)
4643 struct si_ulv_param *ulv = &si_pi->ulv;
4647 ret = si_populate_memory_timing_parameters(rdev, &ulv->pl,
4653 ulv->volt_change_delay);
4678 const struct si_ulv_param *ulv = &si_pi->ulv;
4740 if (ulv->supported && ulv->pl.vddc) {
4749 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control);
4750 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
5119 struct si_ulv_param *ulv = &si_pi->ulv;
5121 if (ulv->supported)
5132 const struct si_ulv_param *ulv = &si_pi->ulv;
5136 if (state->performance_levels[0].mclk != ulv->pl.mclk)
5144 if (ulv->pl.vddc <
5160 const struct si_ulv_param *ulv = &si_pi->ulv;
5162 if (ulv->supported) {
5277 struct si_ulv_param *ulv = &si_pi->ulv;
5280 if (ulv->supported && ulv->pl.vddc) {
5636 struct si_ulv_param *ulv = &si_pi->ulv;
5653 if (ulv->supported && ulv->pl.vddc != 0)
5654 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl,
6754 si_pi->ulv.supported = false;
6755 si_pi->ulv.pl = *pl;
6756 si_pi->ulv.one_pcie_lane_in_ulv = false;
6757 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;
6758 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;
6759 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;