Lines Matching defs:rdev
1725 static int si_populate_voltage_value(struct radeon_device *rdev,
1728 static int si_get_std_voltage_value(struct radeon_device *rdev,
1731 static int si_write_smc_soft_register(struct radeon_device *rdev,
1733 static int si_convert_power_level_to_smc(struct radeon_device *rdev,
1736 static int si_calculate_sclk_params(struct radeon_device *rdev,
1740 static void si_thermal_start_smc_fan_control(struct radeon_device *rdev);
1741 static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev);
1743 static struct si_power_info *si_get_pi(struct radeon_device *rdev)
1745 struct si_power_info *pi = rdev->pm.dpm.priv;
1777 static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev,
1805 static void si_calculate_leakage_for_v(struct radeon_device *rdev,
1816 static void si_update_dte_from_pl2(struct radeon_device *rdev,
1819 u32 p_limit1 = rdev->pm.dpm.tdp_limit;
1820 u32 p_limit2 = rdev->pm.dpm.near_tdp_limit;
1846 static void si_initialize_powertune_defaults(struct radeon_device *rdev)
1848 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1849 struct si_power_info *si_pi = si_get_pi(rdev);
1852 if (rdev->family == CHIP_TAHITI) {
1859 switch (rdev->pdev->device) {
1886 } else if (rdev->family == CHIP_PITCAIRN) {
1887 switch (rdev->pdev->device) {
1923 } else if (rdev->family == CHIP_VERDE) {
1928 switch (rdev->pdev->device) {
1975 } else if (rdev->family == CHIP_OLAND) {
1976 switch (rdev->pdev->device) {
2025 } else if (rdev->family == CHIP_HAINAN) {
2048 si_update_dte_from_pl2(rdev, &si_pi->dte_data);
2072 static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev)
2077 static u32 si_calculate_cac_wintime(struct radeon_device *rdev)
2084 xclk = radeon_get_xclk(rdev);
2102 static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev,
2110 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit)
2113 max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100;
2116 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2117 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit);
2119 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2120 adjustment_delta = rdev->pm.dpm.tdp_limit - *tdp_limit;
2121 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted)
2122 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta;
2135 static int si_populate_smc_tdp_limits(struct radeon_device *rdev,
2138 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2139 struct si_power_info *si_pi = si_get_pi(rdev);
2144 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table;
2145 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2155 ret = si_calculate_adjusted_tdp_limits(rdev,
2157 rdev->pm.dpm.tdp_adjustment,
2170 ret = si_copy_bytes_to_smc(rdev,
2189 ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start,
2200 static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev,
2203 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2204 struct si_power_info *si_pi = si_get_pi(rdev);
2208 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2214 cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000);
2216 cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2218 ret = si_copy_bytes_to_smc(rdev,
2232 static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev,
2254 static bool si_should_disable_uvd_powertune(struct radeon_device *rdev,
2257 struct si_power_info *si_pi = si_get_pi(rdev);
2266 static int si_populate_power_containment_values(struct radeon_device *rdev,
2270 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2271 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2294 disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state);
2329 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2334 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc);
2338 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2343 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc);
2347 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev,
2360 static int si_populate_sq_ramping_values(struct radeon_device *rdev,
2364 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2376 if (rdev->pm.dpm.sq_ramping_threshold == 0)
2398 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) &&
2417 static int si_enable_power_containment(struct radeon_device *rdev,
2421 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2427 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2428 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive);
2437 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive);
2447 static int si_initialize_smc_dte_tables(struct radeon_device *rdev)
2449 struct si_power_info *si_pi = si_get_pi(rdev);
2505 ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables,
2512 static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev,
2515 struct si_power_info *si_pi = si_get_pi(rdev);
2517 &rdev->pm.dpm.dyn_state.cac_leakage_table;
2557 static int si_init_dte_leakage_table(struct radeon_device *rdev,
2562 struct si_power_info *si_pi = si_get_pi(rdev);
2570 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2578 si_calculate_leakage_for_v_and_t(rdev,
2597 static int si_init_simplified_leakage_table(struct radeon_device *rdev,
2601 struct si_power_info *si_pi = si_get_pi(rdev);
2608 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2613 si_calculate_leakage_for_v(rdev,
2632 static int si_initialize_smc_cac_tables(struct radeon_device *rdev)
2634 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2635 struct si_power_info *si_pi = si_get_pi(rdev);
2641 u32 ticks_per_us = radeon_get_xclk(rdev) / 100;
2654 si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage;
2657 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev);
2662 ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min);
2672 ret = si_init_dte_leakage_table(rdev, cac_tables,
2676 ret = si_init_simplified_leakage_table(rdev, cac_tables,
2681 load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;
2697 ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables,
2703 ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us);
2716 static int si_program_cac_config_registers(struct radeon_device *rdev,
2755 static int si_initialize_hardware_cac_manager(struct radeon_device *rdev)
2757 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2758 struct si_power_info *si_pi = si_get_pi(rdev);
2765 ret = si_program_cac_config_registers(rdev, si_pi->lcac_config);
2768 ret = si_program_cac_config_registers(rdev, si_pi->cac_override);
2771 ret = si_program_cac_config_registers(rdev, si_pi->cac_weights);
2778 static int si_enable_smc_cac(struct radeon_device *rdev,
2782 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2783 struct si_power_info *si_pi = si_get_pi(rdev);
2789 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2791 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable);
2796 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac);
2805 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE);
2812 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE);
2814 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac);
2819 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable);
2825 static int si_init_smc_spll_table(struct radeon_device *rdev)
2827 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2828 struct si_power_info *si_pi = si_get_pi(rdev);
2846 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params);
2884 ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start,
2896 static u16 si_get_lower_of_leakage_and_vce_voltage(struct radeon_device *rdev,
2900 struct si_power_info *si_pi = si_get_pi(rdev);
2914 static int si_get_vce_clock_voltage(struct radeon_device *rdev,
2920 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
2941 *voltage = si_get_lower_of_leakage_and_vce_voltage(rdev, *voltage);
2946 static void si_apply_state_adjust_rules(struct radeon_device *rdev,
2959 if (rdev->family == CHIP_HAINAN) {
2960 if ((rdev->pdev->revision == 0x81) ||
2961 (rdev->pdev->revision == 0xC3) ||
2962 (rdev->pdev->device == 0x6664) ||
2963 (rdev->pdev->device == 0x6665) ||
2964 (rdev->pdev->device == 0x6667)) {
2967 if ((rdev->pdev->revision == 0xC3) ||
2968 (rdev->pdev->device == 0x6665)) {
2972 } else if (rdev->family == CHIP_OLAND) {
2973 if ((rdev->pdev->revision == 0xC7) ||
2974 (rdev->pdev->revision == 0x80) ||
2975 (rdev->pdev->revision == 0x81) ||
2976 (rdev->pdev->revision == 0x83) ||
2977 (rdev->pdev->revision == 0x87) ||
2978 (rdev->pdev->device == 0x6604) ||
2979 (rdev->pdev->device == 0x6605)) {
2983 if (rdev->pm.dpm.high_pixelclock_count > 1)
2988 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk;
2989 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk;
2990 si_get_vce_clock_voltage(rdev, rps->evclk, rps->ecclk,
2997 if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
2998 ni_dpm_vblank_too_short(rdev))
3006 if (rdev->pm.dpm.ac_power)
3007 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3009 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3015 if (rdev->pm.dpm.ac_power == false) {
3029 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3031 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3033 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3078 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk)
3079 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk;
3080 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk)
3081 mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk;
3129 btc_adjust_clock_combinations(rdev, max_limits,
3135 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3138 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3141 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3144 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
3145 rdev->clock.current_dispclk,
3150 btc_apply_voltage_delta_rules(rdev,
3158 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
3164 static int si_read_smc_soft_register(struct radeon_device *rdev,
3167 struct si_power_info *si_pi = si_get_pi(rdev);
3169 return si_read_smc_sram_dword(rdev,
3175 static int si_write_smc_soft_register(struct radeon_device *rdev,
3178 struct si_power_info *si_pi = si_get_pi(rdev);
3180 return si_write_smc_sram_dword(rdev,
3185 static bool si_is_special_1gb_platform(struct radeon_device *rdev)
3206 if ((rdev->pdev->device == 0x6819) &&
3213 static void si_get_leakage_vddc(struct radeon_device *rdev)
3215 struct si_power_info *si_pi = si_get_pi(rdev);
3220 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i);
3232 static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev,
3235 struct si_power_info *si_pi = si_get_pi(rdev);
3259 static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
3261 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3294 static void si_enable_auto_throttle_source(struct radeon_device *rdev,
3298 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3303 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3308 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3313 static void si_start_dpm(struct radeon_device *rdev)
3318 static void si_stop_dpm(struct radeon_device *rdev)
3323 static void si_enable_sclk_control(struct radeon_device *rdev, bool enable)
3333 static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev,
3339 ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
3348 static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev)
3350 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);
3355 static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power)
3358 return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
3365 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
3369 return si_send_msg_to_smc(rdev, msg);
3372 static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev)
3374 if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
3377 return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
3381 int si_dpm_force_performance_level(struct radeon_device *rdev,
3384 struct radeon_ps *rps = rdev->pm.dpm.current_ps;
3389 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3392 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
3395 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3398 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)
3401 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3404 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3408 rdev->pm.dpm.forced_level = level;
3414 static int si_set_boot_state(struct radeon_device *rdev)
3416 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
3421 static int si_set_sw_state(struct radeon_device *rdev)
3423 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?
3427 static int si_halt_smc(struct radeon_device *rdev)
3429 if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK)
3432 return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ?
3436 static int si_resume_smc(struct radeon_device *rdev)
3438 if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK)
3441 return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ?
3445 static void si_dpm_start_smc(struct radeon_device *rdev)
3447 si_program_jump_on_start(rdev);
3448 si_start_smc(rdev);
3449 si_start_smc_clock(rdev);
3452 static void si_dpm_stop_smc(struct radeon_device *rdev)
3454 si_reset_smc(rdev);
3455 si_stop_smc_clock(rdev);
3458 static int si_process_firmware_header(struct radeon_device *rdev)
3460 struct si_power_info *si_pi = si_get_pi(rdev);
3464 ret = si_read_smc_sram_dword(rdev,
3473 ret = si_read_smc_sram_dword(rdev,
3482 ret = si_read_smc_sram_dword(rdev,
3491 ret = si_read_smc_sram_dword(rdev,
3500 ret = si_read_smc_sram_dword(rdev,
3509 ret = si_read_smc_sram_dword(rdev,
3518 ret = si_read_smc_sram_dword(rdev,
3527 ret = si_read_smc_sram_dword(rdev,
3536 ret = si_read_smc_sram_dword(rdev,
3548 static void si_read_clock_registers(struct radeon_device *rdev)
3550 struct si_power_info *si_pi = si_get_pi(rdev);
3569 static void si_enable_thermal_protection(struct radeon_device *rdev,
3578 static void si_enable_acpi_power_management(struct radeon_device *rdev)
3584 static int si_enter_ulp_state(struct radeon_device *rdev)
3593 static int si_exit_ulp_state(struct radeon_device *rdev)
3601 for (i = 0; i < rdev->usec_timeout; i++) {
3611 static int si_notify_smc_display_change(struct radeon_device *rdev,
3617 return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ?
3621 static void si_program_response_times(struct radeon_device *rdev)
3627 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
3629 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time;
3637 reference_clock = radeon_get_xclk(rdev);
3643 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly);
3644 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly);
3645 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
3646 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
3649 static void si_program_ds_registers(struct radeon_device *rdev)
3651 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3661 static void si_program_display_gap(struct radeon_device *rdev)
3667 if (rdev->pm.dpm.new_active_crtc_count > 0)
3672 if (rdev->pm.dpm.new_active_crtc_count > 1)
3682 if ((rdev->pm.dpm.new_active_crtc_count > 0) &&
3683 (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) {
3685 for (i = 0; i < rdev->num_crtc; i++) {
3686 if (rdev->pm.dpm.new_active_crtcs & (1 << i))
3689 if (i == rdev->num_crtc)
3703 si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0);
3706 static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
3708 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3719 static void si_setup_bsp(struct radeon_device *rdev)
3721 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3722 u32 xclk = radeon_get_xclk(rdev);
3743 static void si_program_git(struct radeon_device *rdev)
3748 static void si_program_tp(struct radeon_device *rdev)
3768 static void si_program_tpp(struct radeon_device *rdev)
3773 static void si_program_sstp(struct radeon_device *rdev)
3778 static void si_enable_display_gap(struct radeon_device *rdev)
3792 static void si_program_vc(struct radeon_device *rdev)
3794 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3799 static void si_clear_vc(struct radeon_device *rdev)
3839 static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk)
3841 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3859 static int si_upload_firmware(struct radeon_device *rdev)
3861 struct si_power_info *si_pi = si_get_pi(rdev);
3864 si_reset_smc(rdev);
3865 si_stop_smc_clock(rdev);
3867 ret = si_load_smc_ucode(rdev, si_pi->sram_end);
3872 static bool si_validate_phase_shedding_tables(struct radeon_device *rdev,
3899 void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
3916 static int si_get_svi2_voltage_table(struct radeon_device *rdev,
3937 static int si_construct_voltage_tables(struct radeon_device *rdev)
3939 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3940 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3941 struct si_power_info *si_pi = si_get_pi(rdev);
3945 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
3951 si_trim_voltage_table_to_fit_state_table(rdev,
3955 ret = si_get_svi2_voltage_table(rdev,
3956 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3965 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI,
3971 si_trim_voltage_table_to_fit_state_table(rdev,
3976 ret = si_get_svi2_voltage_table(rdev,
3977 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3984 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC,
3998 si_trim_voltage_table_to_fit_state_table(rdev,
4004 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
4017 static void si_populate_smc_voltage_table(struct radeon_device *rdev,
4027 static int si_populate_smc_voltage_tables(struct radeon_device *rdev,
4030 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4031 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4032 struct si_power_info *si_pi = si_get_pi(rdev);
4036 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc,
4038 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd,
4040 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type,
4044 si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table);
4057 si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table);
4065 si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table);
4072 if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table,
4073 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) {
4074 si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table);
4079 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,
4090 static int si_populate_voltage_value(struct radeon_device *rdev,
4110 static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
4113 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4114 struct si_power_info *si_pi = si_get_pi(rdev);
4127 static int si_get_std_voltage_value(struct radeon_device *rdev,
4135 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) {
4136 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) {
4137 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
4140 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4142 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4144 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4146 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4149 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4155 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4157 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4159 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4161 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4164 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4170 if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
4171 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
4178 static int si_populate_std_voltage_value(struct radeon_device *rdev,
4188 static int si_populate_phase_shedding_value(struct radeon_device *rdev,
4207 static int si_init_arb_table_index(struct radeon_device *rdev)
4209 struct si_power_info *si_pi = si_get_pi(rdev);
4213 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end);
4220 return si_write_smc_sram_dword(rdev, si_pi->arb_table_start, tmp, si_pi->sram_end);
4223 static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev)
4225 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
4228 static int si_reset_to_default(struct radeon_device *rdev)
4230 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
4234 static int si_force_switch_to_arb_f0(struct radeon_device *rdev)
4236 struct si_power_info *si_pi = si_get_pi(rdev);
4240 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start,
4250 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
4253 static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev,
4272 static int si_populate_memory_timing_parameters(struct radeon_device *rdev,
4281 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk);
4283 radeon_atom_set_engine_dram_timings(rdev,
4298 static int si_do_program_memory_timing_parameters(struct radeon_device *rdev,
4302 struct si_power_info *si_pi = si_get_pi(rdev);
4308 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs);
4311 ret = si_copy_bytes_to_smc(rdev,
4325 static int si_program_memory_timing_parameters(struct radeon_device *rdev,
4328 return si_do_program_memory_timing_parameters(rdev, radeon_new_state,
4332 static int si_populate_initial_mvdd_value(struct radeon_device *rdev,
4335 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4336 struct si_power_info *si_pi = si_get_pi(rdev);
4339 return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table,
4345 static int si_populate_smc_initial_state(struct radeon_device *rdev,
4350 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4351 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4352 struct si_power_info *si_pi = si_get_pi(rdev);
4399 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4406 ret = si_get_std_voltage_value(rdev,
4410 si_populate_std_voltage_value(rdev, std_vddc,
4416 si_populate_voltage_value(rdev,
4422 si_populate_phase_shedding_value(rdev,
4423 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4429 si_populate_initial_mvdd_value(rdev, &table->initialState.level.mvdd);
4440 si_get_strobe_mode_settings(rdev,
4468 static int si_populate_smc_acpi_state(struct radeon_device *rdev,
4471 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4472 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4473 struct si_power_info *si_pi = si_get_pi(rdev);
4493 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4498 ret = si_get_std_voltage_value(rdev,
4501 si_populate_std_voltage_value(rdev, std_vddc,
4508 si_populate_phase_shedding_value(rdev,
4509 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4516 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4521 ret = si_get_std_voltage_value(rdev,
4525 si_populate_std_voltage_value(rdev, std_vddc,
4529 table->ACPIState.level.gen2PCIE = (u8)r600_get_pcie_gen_support(rdev,
4535 si_populate_phase_shedding_value(rdev,
4536 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4545 si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
4589 si_populate_mvdd_value(rdev, 0, &table->ACPIState.level.mvdd);
4609 static int si_populate_ulv_state(struct radeon_device *rdev,
4612 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4613 struct si_power_info *si_pi = si_get_pi(rdev);
4618 ret = si_convert_power_level_to_smc(rdev, &ulv->pl,
4640 static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev)
4642 struct si_power_info *si_pi = si_get_pi(rdev);
4647 ret = si_populate_memory_timing_parameters(rdev, &ulv->pl,
4652 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,
4655 ret = si_copy_bytes_to_smc(rdev,
4666 static void si_get_mvdd_configuration(struct radeon_device *rdev)
4668 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4673 static int si_init_smc_table(struct radeon_device *rdev)
4675 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4676 struct si_power_info *si_pi = si_get_pi(rdev);
4677 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
4684 si_populate_smc_voltage_tables(rdev, table);
4686 switch (rdev->pm.int_thermal_type) {
4699 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
4702 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) {
4703 if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819))
4707 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
4713 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)
4716 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) {
4718 vr_hot_gpio = rdev->pm.dpm.backbias_response_time;
4719 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio,
4723 ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table);
4727 ret = si_populate_smc_acpi_state(rdev, table);
4735 ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state,
4741 ret = si_populate_ulv_state(rdev, &table->ULVState);
4745 ret = si_program_ulv_memory_timing_parameters(rdev);
4752 lane_width = radeon_get_pcie_lanes(rdev);
4753 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
4758 return si_copy_bytes_to_smc(rdev, si_pi->state_table_start,
4763 static int si_calculate_sclk_params(struct radeon_device *rdev,
4767 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4768 struct si_power_info *si_pi = si_get_pi(rdev);
4777 u32 reference_clock = rdev->clock.spll.reference_freq;
4782 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
4808 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4833 static int si_populate_sclk_value(struct radeon_device *rdev,
4840 ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp);
4854 static int si_populate_mclk_value(struct radeon_device *rdev,
4861 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4862 struct si_power_info *si_pi = si_get_pi(rdev);
4875 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param);
4899 u32 reference_clock = rdev->clock.mpll.reference_freq;
4908 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4943 static void si_populate_smc_sp(struct radeon_device *rdev,
4948 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4958 static int si_convert_power_level_to_smc(struct radeon_device *rdev,
4962 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4963 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4964 struct si_power_info *si_pi = si_get_pi(rdev);
4976 ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk);
4986 (rdev->pm.dpm.new_active_crtc_count <= 2)) {
5000 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk);
5012 level->strobeMode = si_get_strobe_mode_settings(rdev,
5018 ret = si_populate_mclk_value(rdev,
5026 ret = si_populate_voltage_value(rdev,
5033 ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc);
5037 ret = si_populate_std_voltage_value(rdev, std_vddc,
5043 ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
5050 ret = si_populate_phase_shedding_value(rdev,
5051 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
5062 ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd);
5067 static int si_populate_smc_t(struct radeon_device *rdev,
5071 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5116 static int si_disable_ulv(struct radeon_device *rdev)
5118 struct si_power_info *si_pi = si_get_pi(rdev);
5122 return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
5128 static bool si_is_state_ulv_compatible(struct radeon_device *rdev,
5131 const struct si_power_info *si_pi = si_get_pi(rdev);
5141 for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) {
5142 if (rdev->clock.current_dispclk <=
5143 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) {
5145 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v)
5156 static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev,
5159 const struct si_power_info *si_pi = si_get_pi(rdev);
5163 if (si_is_state_ulv_compatible(rdev, radeon_new_state))
5164 return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
5170 static int si_convert_power_state_to_smc(struct radeon_device *rdev,
5174 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5175 struct ni_power_info *ni_pi = ni_get_pi(rdev);
5176 struct si_power_info *si_pi = si_get_pi(rdev);
5209 ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i],
5233 si_write_smc_soft_register(rdev,
5237 si_populate_smc_sp(rdev, radeon_state, smc_state);
5239 ret = si_populate_power_containment_values(rdev, radeon_state, smc_state);
5243 ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state);
5247 return si_populate_smc_t(rdev, radeon_state, smc_state);
5250 static int si_upload_sw_state(struct radeon_device *rdev,
5253 struct si_power_info *si_pi = si_get_pi(rdev);
5264 ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state);
5268 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5274 static int si_upload_ulv_state(struct radeon_device *rdev)
5276 struct si_power_info *si_pi = si_get_pi(rdev);
5288 ret = si_populate_ulv_state(rdev, smc_state);
5290 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5297 static int si_upload_smc_data(struct radeon_device *rdev)
5302 if (rdev->pm.dpm.new_active_crtc_count == 0)
5305 for (i = 0; i < rdev->num_crtc; i++) {
5306 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) {
5307 radeon_crtc = rdev->mode_info.crtcs[i];
5318 if (si_write_smc_soft_register(rdev,
5323 if (si_write_smc_soft_register(rdev,
5328 if (si_write_smc_soft_register(rdev,
5336 static int si_set_mc_special_registers(struct radeon_device *rdev,
5339 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5513 static int si_initialize_mc_reg_table(struct radeon_device *rdev)
5515 struct si_power_info *si_pi = si_get_pi(rdev);
5518 u8 module_index = rv770_get_memory_module_index(rdev);
5540 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
5550 ret = si_set_mc_special_registers(rdev, si_table);
5563 static void si_populate_mc_reg_addresses(struct radeon_device *rdev,
5566 struct si_power_info *si_pi = si_get_pi(rdev);
5597 static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
5601 struct si_power_info *si_pi = si_get_pi(rdev);
5617 static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
5625 si_convert_mc_reg_table_entry_to_smc(rdev,
5631 static int si_populate_mc_reg_table(struct radeon_device *rdev,
5635 struct si_power_info *si_pi = si_get_pi(rdev);
5641 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1);
5643 si_populate_mc_reg_addresses(rdev, smc_mc_reg_table);
5645 si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0],
5654 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl,
5662 si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table);
5664 return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start,
5669 static int si_upload_mc_reg_table(struct radeon_device *rdev,
5673 struct si_power_info *si_pi = si_get_pi(rdev);
5681 si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table);
5684 return si_copy_bytes_to_smc(rdev, address,
5691 static void si_enable_voltage_control(struct radeon_device *rdev, bool enable)
5699 static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev,
5714 static u16 si_get_current_pcie_speed(struct radeon_device *rdev)
5724 static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev,
5728 struct si_power_info *si_pi = si_get_pi(rdev);
5729 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5733 current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state);
5743 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
5750 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
5755 si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev);
5764 static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev,
5768 struct si_power_info *si_pi = si_get_pi(rdev);
5769 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5781 (si_get_current_pcie_speed(rdev) > 0))
5785 radeon_acpi_pcie_performance_request(rdev, request, false);
5791 static int si_ds_request(struct radeon_device *rdev,
5794 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5798 return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
5802 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
5809 static void si_set_max_cu_value(struct radeon_device *rdev)
5811 struct si_power_info *si_pi = si_get_pi(rdev);
5813 if (rdev->family == CHIP_VERDE) {
5814 switch (rdev->pdev->device) {
5850 static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev,
5859 switch (si_get_leakage_voltage_from_leakage_index(rdev,
5881 static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev)
5885 ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5886 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
5887 ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5888 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
5889 ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5890 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
5894 static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev,
5905 radeon_set_pcie_lanes(rdev, new_lane_width);
5906 lane_width = radeon_get_pcie_lanes(rdev);
5907 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
5911 static void si_set_vce_clock(struct radeon_device *rdev,
5919 vce_v1_0_enable_mgcg(rdev, false);
5921 vce_v1_0_enable_mgcg(rdev, true);
5922 radeon_set_vce_clocks(rdev, new_rps->evclk, new_rps->ecclk);
5926 void si_dpm_setup_asic(struct radeon_device *rdev)
5930 r = si_mc_load_microcode(rdev);
5933 rv770_get_memory_type(rdev);
5934 si_read_clock_registers(rdev);
5935 si_enable_acpi_power_management(rdev);
5938 static int si_thermal_enable_alert(struct radeon_device *rdev,
5948 rdev->irq.dpm_thermal = false;
5949 result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
5957 rdev->irq.dpm_thermal = true;
5963 static int si_thermal_set_temperature_range(struct radeon_device *rdev,
5982 rdev->pm.dpm.thermal.min_temp = low_temp;
5983 rdev->pm.dpm.thermal.max_temp = high_temp;
5988 static void si_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode)
5990 struct si_power_info *si_pi = si_get_pi(rdev);
6010 static int si_thermal_setup_fan_table(struct radeon_device *rdev)
6012 struct si_power_info *si_pi = si_get_pi(rdev);
6022 rdev->pm.dpm.fan.ucode_fan_control = false;
6029 rdev->pm.dpm.fan.ucode_fan_control = false;
6033 tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100;
6037 t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min;
6038 t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med;
6040 pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min;
6041 pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med;
6046 fan_table.temp_min = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100);
6047 fan_table.temp_med = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100);
6048 fan_table.temp_max = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100);
6055 fan_table.hys_down = cpu_to_be16(rdev->pm.dpm.fan.t_hyst);
6063 reference_clock = radeon_get_xclk(rdev);
6065 fan_table.refresh_period = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay *
6073 ret = si_copy_bytes_to_smc(rdev,
6081 rdev->pm.dpm.fan.ucode_fan_control = false;
6087 static int si_fan_ctrl_start_smc_fan_control(struct radeon_device *rdev)
6089 struct si_power_info *si_pi = si_get_pi(rdev);
6092 ret = si_send_msg_to_smc(rdev, PPSMC_StartFanControl);
6101 static int si_fan_ctrl_stop_smc_fan_control(struct radeon_device *rdev)
6103 struct si_power_info *si_pi = si_get_pi(rdev);
6106 ret = si_send_msg_to_smc(rdev, PPSMC_StopFanControl);
6116 int si_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev,
6122 if (rdev->pm.no_fan)
6141 int si_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev,
6144 struct si_power_info *si_pi = si_get_pi(rdev);
6149 if (rdev->pm.no_fan)
6174 void si_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode)
6178 if (rdev->pm.dpm.fan.ucode_fan_control)
6179 si_fan_ctrl_stop_smc_fan_control(rdev);
6180 si_fan_ctrl_set_static_mode(rdev, mode);
6183 if (rdev->pm.dpm.fan.ucode_fan_control)
6184 si_thermal_start_smc_fan_control(rdev);
6186 si_fan_ctrl_set_default_mode(rdev);
6190 u32 si_fan_ctrl_get_mode(struct radeon_device *rdev)
6192 struct si_power_info *si_pi = si_get_pi(rdev);
6203 static int si_fan_ctrl_get_fan_speed_rpm(struct radeon_device *rdev,
6207 u32 xclk = radeon_get_xclk(rdev);
6209 if (rdev->pm.no_fan)
6212 if (rdev->pm.fan_pulses_per_revolution == 0)
6224 static int si_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev,
6228 u32 xclk = radeon_get_xclk(rdev);
6230 if (rdev->pm.no_fan)
6233 if (rdev->pm.fan_pulses_per_revolution == 0)
6236 if ((speed < rdev->pm.fan_min_rpm) ||
6237 (speed > rdev->pm.fan_max_rpm))
6240 if (rdev->pm.dpm.fan.ucode_fan_control)
6241 si_fan_ctrl_stop_smc_fan_control(rdev);
6248 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC_RPM);
6254 static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev)
6256 struct si_power_info *si_pi = si_get_pi(rdev);
6271 static void si_thermal_start_smc_fan_control(struct radeon_device *rdev)
6273 if (rdev->pm.dpm.fan.ucode_fan_control) {
6274 si_fan_ctrl_start_smc_fan_control(rdev);
6275 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC);
6279 static void si_thermal_initialize(struct radeon_device *rdev)
6283 if (rdev->pm.fan_pulses_per_revolution) {
6285 tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1);
6294 static int si_thermal_start_thermal_controller(struct radeon_device *rdev)
6298 si_thermal_initialize(rdev);
6299 ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6302 ret = si_thermal_enable_alert(rdev, true);
6305 if (rdev->pm.dpm.fan.ucode_fan_control) {
6306 ret = si_halt_smc(rdev);
6309 ret = si_thermal_setup_fan_table(rdev);
6312 ret = si_resume_smc(rdev);
6315 si_thermal_start_smc_fan_control(rdev);
6321 static void si_thermal_stop_thermal_controller(struct radeon_device *rdev)
6323 if (!rdev->pm.no_fan) {
6324 si_fan_ctrl_set_default_mode(rdev);
6325 si_fan_ctrl_stop_smc_fan_control(rdev);
6329 int si_dpm_enable(struct radeon_device *rdev)
6331 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6332 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6333 struct si_power_info *si_pi = si_get_pi(rdev);
6334 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
6337 if (si_is_smc_running(rdev))
6340 si_enable_voltage_control(rdev, true);
6342 si_get_mvdd_configuration(rdev);
6344 ret = si_construct_voltage_tables(rdev);
6351 ret = si_initialize_mc_reg_table(rdev);
6356 si_enable_spread_spectrum(rdev, true);
6358 si_enable_thermal_protection(rdev, true);
6359 si_setup_bsp(rdev);
6360 si_program_git(rdev);
6361 si_program_tp(rdev);
6362 si_program_tpp(rdev);
6363 si_program_sstp(rdev);
6364 si_enable_display_gap(rdev);
6365 si_program_vc(rdev);
6366 ret = si_upload_firmware(rdev);
6371 ret = si_process_firmware_header(rdev);
6376 ret = si_initial_switch_from_arb_f0_to_f1(rdev);
6381 ret = si_init_smc_table(rdev);
6386 ret = si_init_smc_spll_table(rdev);
6391 ret = si_init_arb_table_index(rdev);
6397 ret = si_populate_mc_reg_table(rdev, boot_ps);
6403 ret = si_initialize_smc_cac_tables(rdev);
6408 ret = si_initialize_hardware_cac_manager(rdev);
6413 ret = si_initialize_smc_dte_tables(rdev);
6418 ret = si_populate_smc_tdp_limits(rdev, boot_ps);
6423 ret = si_populate_smc_tdp_limits_2(rdev, boot_ps);
6428 si_program_response_times(rdev);
6429 si_program_ds_registers(rdev);
6430 si_dpm_start_smc(rdev);
6431 ret = si_notify_smc_display_change(rdev, false);
6436 si_enable_sclk_control(rdev, true);
6437 si_start_dpm(rdev);
6439 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
6441 si_thermal_start_thermal_controller(rdev);
6443 ni_update_current_ps(rdev, boot_ps);
6448 static int si_set_temperature_range(struct radeon_device *rdev)
6452 ret = si_thermal_enable_alert(rdev, false);
6455 ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6458 ret = si_thermal_enable_alert(rdev, true);
6465 int si_dpm_late_enable(struct radeon_device *rdev)
6469 ret = si_set_temperature_range(rdev);
6476 void si_dpm_disable(struct radeon_device *rdev)
6478 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6479 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
6481 if (!si_is_smc_running(rdev))
6483 si_thermal_stop_thermal_controller(rdev);
6484 si_disable_ulv(rdev);
6485 si_clear_vc(rdev);
6487 si_enable_thermal_protection(rdev, false);
6488 si_enable_power_containment(rdev, boot_ps, false);
6489 si_enable_smc_cac(rdev, boot_ps, false);
6490 si_enable_spread_spectrum(rdev, false);
6491 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
6492 si_stop_dpm(rdev);
6493 si_reset_to_default(rdev);
6494 si_dpm_stop_smc(rdev);
6495 si_force_switch_to_arb_f0(rdev);
6497 ni_update_current_ps(rdev, boot_ps);
6500 int si_dpm_pre_set_power_state(struct radeon_device *rdev)
6502 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6503 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
6506 ni_update_requested_ps(rdev, new_ps);
6508 si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps);
6513 static int si_power_control_set_level(struct radeon_device *rdev)
6515 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
6518 ret = si_restrict_performance_levels_before_switch(rdev);
6521 ret = si_halt_smc(rdev);
6524 ret = si_populate_smc_tdp_limits(rdev, new_ps);
6527 ret = si_populate_smc_tdp_limits_2(rdev, new_ps);
6530 ret = si_resume_smc(rdev);
6533 ret = si_set_sw_state(rdev);
6539 int si_dpm_set_power_state(struct radeon_device *rdev)
6541 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6546 ret = si_disable_ulv(rdev);
6551 ret = si_restrict_performance_levels_before_switch(rdev);
6557 si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps);
6558 ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
6559 ret = si_enable_power_containment(rdev, new_ps, false);
6564 ret = si_enable_smc_cac(rdev, new_ps, false);
6569 ret = si_halt_smc(rdev);
6574 ret = si_upload_sw_state(rdev, new_ps);
6579 ret = si_upload_smc_data(rdev);
6584 ret = si_upload_ulv_state(rdev);
6590 ret = si_upload_mc_reg_table(rdev, new_ps);
6596 ret = si_program_memory_timing_parameters(rdev, new_ps);
6601 si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps);
6603 ret = si_resume_smc(rdev);
6608 ret = si_set_sw_state(rdev);
6613 ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
6614 si_set_vce_clock(rdev, new_ps, old_ps);
6616 si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
6617 ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps);
6622 ret = si_enable_smc_cac(rdev, new_ps, true);
6627 ret = si_enable_power_containment(rdev, new_ps, true);
6633 ret = si_power_control_set_level(rdev);
6642 void si_dpm_post_set_power_state(struct radeon_device *rdev)
6644 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6647 ni_update_current_ps(rdev, new_ps);
6651 void si_dpm_reset_asic(struct radeon_device *rdev)
6653 si_restrict_performance_levels_before_switch(rdev);
6654 si_disable_ulv(rdev);
6655 si_set_boot_state(rdev);
6659 void si_dpm_display_configuration_changed(struct radeon_device *rdev)
6661 si_program_display_gap(rdev);
6686 static void si_parse_pplib_non_clock_info(struct radeon_device *rdev,
6707 rdev->pm.dpm.boot_ps = rps;
6709 rdev->pm.dpm.uvd_ps = rps;
6712 static void si_parse_pplib_clock_info(struct radeon_device *rdev,
6716 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6717 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6718 struct si_power_info *si_pi = si_get_pi(rdev);
6734 pl->pcie_gen = r600_get_pcie_gen_support(rdev,
6740 ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc,
6771 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
6772 pl->mclk = rdev->clock.default_mclk;
6773 pl->sclk = rdev->clock.default_sclk;
6781 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
6782 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
6783 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
6784 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
6788 static int si_parse_power_table(struct radeon_device *rdev)
6790 struct radeon_mode_info *mode_info = &rdev->mode_info;
6820 rdev->pm.dpm.ps = kcalloc(state_array->ucNumEntries,
6823 if (!rdev->pm.dpm.ps)
6832 if (!rdev->pm.power_state[i].clock_info)
6836 kfree(rdev->pm.dpm.ps);
6839 rdev->pm.dpm.ps[i].ps_priv = ps;
6840 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
6854 si_parse_pplib_clock_info(rdev,
6855 &rdev->pm.dpm.ps[i], k,
6861 rdev->pm.dpm.num_ps = state_array->ucNumEntries;
6866 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx;
6873 rdev->pm.dpm.vce_states[i].sclk = sclk;
6874 rdev->pm.dpm.vce_states[i].mclk = mclk;
6880 int si_dpm_init(struct radeon_device *rdev)
6888 struct pci_dev *root = rdev->pdev->bus->self;
6894 rdev->pm.dpm.priv = si_pi;
6899 if (!pci_is_root_bus(rdev->pdev->bus))
6915 si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev);
6917 si_set_max_cu_value(rdev);
6919 rv770_get_max_vddc(rdev);
6920 si_get_leakage_vddc(rdev);
6921 si_patch_dependency_tables_based_on_leakage(rdev);
6928 ret = r600_get_platform_caps(rdev);
6932 ret = r600_parse_extended_power_table(rdev);
6936 ret = si_parse_power_table(rdev);
6940 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
6944 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
6945 r600_free_extended_power_table(rdev);
6948 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
6949 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
6950 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
6951 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
6952 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
6953 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
6954 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
6955 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
6956 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
6958 if (rdev->pm.dpm.voltage_response_time == 0)
6959 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
6960 if (rdev->pm.dpm.backbias_response_time == 0)
6961 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
6963 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
6973 if (si_is_special_1gb_platform(rdev))
6983 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
6987 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
6990 radeon_atom_get_svi2_info(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
6995 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC,
6999 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7003 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7007 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7010 rv770_get_engine_memory_ss(rdev);
7021 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
7031 radeon_acpi_is_pcie_performance_request_supported(rdev);
7038 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
7039 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
7040 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
7041 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
7042 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
7043 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
7044 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
7046 si_initialize_powertune_defaults(rdev);
7049 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
7050 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
7051 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
7052 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
7059 void si_dpm_fini(struct radeon_device *rdev)
7063 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
7064 kfree(rdev->pm.dpm.ps[i].ps_priv);
7066 kfree(rdev->pm.dpm.ps);
7067 kfree(rdev->pm.dpm.priv);
7068 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
7069 r600_free_extended_power_table(rdev);
7072 void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
7075 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
7093 u32 si_dpm_get_current_sclk(struct radeon_device *rdev)
7095 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
7111 u32 si_dpm_get_current_mclk(struct radeon_device *rdev)
7113 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);