Lines Matching defs:rdev
56 struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev)
58 struct rv7xx_power_info *pi = rdev->pm.dpm.priv;
63 struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev)
65 struct evergreen_power_info *pi = rdev->pm.dpm.priv;
70 static void rv770_enable_bif_dynamic_pcie_gen2(struct radeon_device *rdev,
73 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
93 static void rv770_enable_l0s(struct radeon_device *rdev)
102 static void rv770_enable_l1(struct radeon_device *rdev)
114 static void rv770_enable_pll_sleep_in_l1(struct radeon_device *rdev)
131 static void rv770_gfx_clock_gating_enable(struct radeon_device *rdev,
144 static void rv770_mg_clock_gating_enable(struct radeon_device *rdev,
147 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
152 if (rdev->family == CHIP_RV770)
168 void rv770_restore_cgcg(struct radeon_device *rdev)
181 static void rv770_start_dpm(struct radeon_device *rdev)
190 void rv770_stop_dpm(struct radeon_device *rdev)
194 result = rv770_send_msg_to_smc(rdev, PPSMC_MSG_TwoLevelsDisabled);
206 bool rv770_dpm_enabled(struct radeon_device *rdev)
214 void rv770_enable_thermal_protection(struct radeon_device *rdev,
223 void rv770_enable_acpi_pm(struct radeon_device *rdev)
228 u8 rv770_get_seq_value(struct radeon_device *rdev,
236 int rv770_read_smc_soft_register(struct radeon_device *rdev,
239 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
241 return rv770_read_smc_sram_dword(rdev,
247 int rv770_write_smc_soft_register(struct radeon_device *rdev,
250 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
252 return rv770_write_smc_sram_dword(rdev,
257 int rv770_populate_smc_t(struct radeon_device *rdev,
262 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
303 int rv770_populate_smc_sp(struct radeon_device *rdev,
307 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
372 u32 rv770_map_clkf_to_ibias(struct radeon_device *rdev, u32 clkf)
387 static int rv770_populate_mclk_value(struct radeon_device *rdev,
391 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
405 u32 reference_clock = rdev->clock.mpll.reference_freq;
411 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM,
427 ibias = rv770_map_clkf_to_ibias(rdev, clkf);
451 ibias = rv770_map_clkf_to_ibias(rdev, clkf);
485 static int rv770_populate_sclk_value(struct radeon_device *rdev,
489 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
502 u32 reference_clock = rdev->clock.spll.reference_freq;
507 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
543 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
567 int rv770_populate_vddc_value(struct radeon_device *rdev, u16 vddc,
570 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
593 int rv770_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
596 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
615 static int rv770_convert_power_level_to_smc(struct radeon_device *rdev,
620 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
629 if (rdev->family == CHIP_RV740)
630 ret = rv740_populate_sclk_value(rdev, pl->sclk,
632 else if ((rdev->family == CHIP_RV730) || (rdev->family == CHIP_RV710))
633 ret = rv730_populate_sclk_value(rdev, pl->sclk,
636 ret = rv770_populate_sclk_value(rdev, pl->sclk,
641 if (rdev->family == CHIP_RV740) {
654 ret = rv740_populate_mclk_value(rdev, pl->sclk,
656 } else if ((rdev->family == CHIP_RV730) || (rdev->family == CHIP_RV710))
657 ret = rv730_populate_mclk_value(rdev, pl->sclk,
660 ret = rv770_populate_mclk_value(rdev, pl->sclk,
665 ret = rv770_populate_vddc_value(rdev, pl->vddc,
670 ret = rv770_populate_mvdd_value(rdev, pl->mclk, &level->mvdd);
675 static int rv770_convert_power_state_to_smc(struct radeon_device *rdev,
685 ret = rv770_convert_power_level_to_smc(rdev,
692 ret = rv770_convert_power_level_to_smc(rdev,
699 ret = rv770_convert_power_level_to_smc(rdev,
710 smc_state->levels[0].seqValue = rv770_get_seq_value(rdev,
712 smc_state->levels[1].seqValue = rv770_get_seq_value(rdev,
714 smc_state->levels[2].seqValue = rv770_get_seq_value(rdev,
717 rv770_populate_smc_sp(rdev, radeon_state, smc_state);
719 return rv770_populate_smc_t(rdev, radeon_state, smc_state);
723 u32 rv770_calculate_memory_refresh_rate(struct radeon_device *rdev,
740 static void rv770_program_memory_timing_parameters(struct radeon_device *rdev,
744 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
754 radeon_atom_set_engine_dram_timings(rdev, high_clock,
765 POWERMODE0(rv770_calculate_memory_refresh_rate(rdev, pi->boot_sclk)) |
766 POWERMODE1(rv770_calculate_memory_refresh_rate(rdev, state->low.sclk)) |
767 POWERMODE2(rv770_calculate_memory_refresh_rate(rdev, state->medium.sclk)) |
768 POWERMODE3(rv770_calculate_memory_refresh_rate(rdev, state->high.sclk));
772 void rv770_enable_backbias(struct radeon_device *rdev,
781 static void rv770_enable_spread_spectrum(struct radeon_device *rdev,
784 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
791 if (rdev->family == CHIP_RV740)
792 rv740_enable_mclk_spread_spectrum(rdev, true);
801 if (rdev->family == CHIP_RV740)
802 rv740_enable_mclk_spread_spectrum(rdev, false);
806 static void rv770_program_mpll_timing_parameters(struct radeon_device *rdev)
808 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
810 if ((rdev->family == CHIP_RV770) && !pi->mem_gddr5) {
817 void rv770_setup_bsp(struct radeon_device *rdev)
819 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
820 u32 xclk = radeon_get_xclk(rdev);
841 void rv770_program_git(struct radeon_device *rdev)
846 void rv770_program_tp(struct radeon_device *rdev)
864 void rv770_program_tpp(struct radeon_device *rdev)
869 void rv770_program_sstp(struct radeon_device *rdev)
874 void rv770_program_engine_speed_parameters(struct radeon_device *rdev)
879 static void rv770_enable_display_gap(struct radeon_device *rdev)
889 void rv770_program_vc(struct radeon_device *rdev)
891 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
896 void rv770_clear_vc(struct radeon_device *rdev)
901 int rv770_upload_firmware(struct radeon_device *rdev)
903 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
906 rv770_reset_smc(rdev);
907 rv770_stop_smc_clock(rdev);
909 ret = rv770_load_smc_ucode(rdev, pi->sram_end);
916 static int rv770_populate_smc_acpi_state(struct radeon_device *rdev,
919 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
943 rv770_populate_vddc_value(rdev, pi->acpi_vddc,
957 rv770_populate_vddc_value(rdev, pi->min_vddc_in_table,
999 rv770_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
1007 int rv770_populate_initial_mvdd_value(struct radeon_device *rdev,
1010 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1024 static int rv770_populate_smc_initial_state(struct radeon_device *rdev,
1029 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1070 rv770_get_seq_value(rdev, &initial_state->low);
1072 rv770_populate_vddc_value(rdev,
1075 rv770_populate_initial_mvdd_value(rdev,
1092 if (rdev->family == CHIP_RV740) {
1115 static int rv770_populate_smc_vddc_table(struct radeon_device *rdev,
1118 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1144 static int rv770_populate_smc_mvdd_table(struct radeon_device *rdev,
1147 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1163 static int rv770_init_smc_table(struct radeon_device *rdev,
1166 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1175 rv770_populate_smc_vddc_table(rdev, table);
1176 rv770_populate_smc_mvdd_table(rdev, table);
1178 switch (rdev->pm.int_thermal_type) {
1192 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) {
1195 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_DONT_WAIT_FOR_VBLANK_ON_ALERT)
1198 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_GOTO_BOOT_ON_ALERT)
1202 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
1208 if ((rdev->family == CHIP_RV730) || (rdev->family == CHIP_RV710))
1209 ret = rv730_populate_smc_initial_state(rdev, radeon_boot_state, table);
1211 ret = rv770_populate_smc_initial_state(rdev, radeon_boot_state, table);
1215 if (rdev->family == CHIP_RV740)
1216 ret = rv740_populate_smc_acpi_state(rdev, table);
1217 else if ((rdev->family == CHIP_RV730) || (rdev->family == CHIP_RV710))
1218 ret = rv730_populate_smc_acpi_state(rdev, table);
1220 ret = rv770_populate_smc_acpi_state(rdev, table);
1226 return rv770_copy_bytes_to_smc(rdev,
1233 static int rv770_construct_vddc_table(struct radeon_device *rdev)
1235 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1241 radeon_atom_get_min_voltage(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, &min);
1242 radeon_atom_get_max_voltage(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, &max);
1243 radeon_atom_get_voltage_step(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, &step);
1254 radeon_atom_get_voltage_gpio_settings(rdev,
1284 static int rv770_get_mvdd_pin_configuration(struct radeon_device *rdev)
1286 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1289 radeon_atom_get_voltage_gpio_settings(rdev,
1296 radeon_atom_get_voltage_gpio_settings(rdev,
1305 u8 rv770_get_memory_module_index(struct radeon_device *rdev)
1310 static int rv770_get_mvdd_configuration(struct radeon_device *rdev)
1312 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1316 memory_module_index = rv770_get_memory_module_index(rdev);
1318 if (radeon_atom_get_memory_info(rdev, memory_module_index, &memory_info)) {
1331 return rv770_get_mvdd_pin_configuration(rdev);
1334 void rv770_enable_voltage_control(struct radeon_device *rdev,
1343 static void rv770_program_display_gap(struct radeon_device *rdev)
1348 if (rdev->pm.dpm.new_active_crtcs & 1) {
1351 } else if (rdev->pm.dpm.new_active_crtcs & 2) {
1361 static void rv770_enable_dynamic_pcie_gen2(struct radeon_device *rdev,
1364 rv770_enable_bif_dynamic_pcie_gen2(rdev, enable);
1372 static void r7xx_program_memory_timing_parameters(struct radeon_device *rdev,
1375 if ((rdev->family == CHIP_RV730) ||
1376 (rdev->family == CHIP_RV710) ||
1377 (rdev->family == CHIP_RV740))
1378 rv730_program_memory_timing_parameters(rdev, radeon_new_state);
1380 rv770_program_memory_timing_parameters(rdev, radeon_new_state);
1383 static int rv770_upload_sw_state(struct radeon_device *rdev,
1386 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1392 ret = rv770_convert_power_state_to_smc(rdev, radeon_new_state, &state);
1396 return rv770_copy_bytes_to_smc(rdev, address, (const u8 *)&state,
1401 int rv770_halt_smc(struct radeon_device *rdev)
1403 if (rv770_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK)
1406 if (rv770_wait_for_smc_inactive(rdev) != PPSMC_Result_OK)
1412 int rv770_resume_smc(struct radeon_device *rdev)
1414 if (rv770_send_msg_to_smc(rdev, PPSMC_MSG_Resume) != PPSMC_Result_OK)
1419 int rv770_set_sw_state(struct radeon_device *rdev)
1421 if (rv770_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) != PPSMC_Result_OK)
1426 int rv770_set_boot_state(struct radeon_device *rdev)
1428 if (rv770_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) != PPSMC_Result_OK)
1433 void rv770_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev,
1447 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
1450 void rv770_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev,
1464 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
1467 int rv770_restrict_performance_levels_before_switch(struct radeon_device *rdev)
1469 if (rv770_send_msg_to_smc(rdev, (PPSMC_Msg)(PPSMC_MSG_NoForcedLevel)) != PPSMC_Result_OK)
1472 if (rv770_send_msg_to_smc(rdev, (PPSMC_Msg)(PPSMC_MSG_TwoLevelsDisabled)) != PPSMC_Result_OK)
1478 int rv770_dpm_force_performance_level(struct radeon_device *rdev,
1484 if (rv770_send_msg_to_smc(rdev, PPSMC_MSG_ZeroLevelsDisabled) != PPSMC_Result_OK)
1488 if (rv770_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
1492 if (rv770_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
1497 if (rv770_send_msg_to_smc(rdev, msg) != PPSMC_Result_OK)
1500 rdev->pm.dpm.forced_level = level;
1505 void r7xx_start_smc(struct radeon_device *rdev)
1507 rv770_start_smc(rdev);
1508 rv770_start_smc_clock(rdev);
1512 void r7xx_stop_smc(struct radeon_device *rdev)
1514 rv770_reset_smc(rdev);
1515 rv770_stop_smc_clock(rdev);
1518 static void rv770_read_clock_registers(struct radeon_device *rdev)
1520 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1545 static void r7xx_read_clock_registers(struct radeon_device *rdev)
1547 if (rdev->family == CHIP_RV740)
1548 rv740_read_clock_registers(rdev);
1549 else if ((rdev->family == CHIP_RV730) || (rdev->family == CHIP_RV710))
1550 rv730_read_clock_registers(rdev);
1552 rv770_read_clock_registers(rdev);
1555 void rv770_read_voltage_smio_registers(struct radeon_device *rdev)
1557 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1563 void rv770_reset_smio_status(struct radeon_device *rdev)
1565 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1591 void rv770_get_memory_type(struct radeon_device *rdev)
1593 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1606 void rv770_get_pcie_gen2_status(struct radeon_device *rdev)
1608 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1629 static int rv770_enter_ulp_state(struct radeon_device *rdev)
1631 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1648 static int rv770_exit_ulp_state(struct radeon_device *rdev)
1650 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1658 for (i = 0; i < rdev->usec_timeout; i++) {
1671 static void rv770_get_mclk_odt_threshold(struct radeon_device *rdev)
1673 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1679 if ((rdev->family == CHIP_RV730) || (rdev->family == CHIP_RV710)) {
1680 memory_module_index = rv770_get_memory_module_index(rdev);
1682 if (radeon_atom_get_memory_info(rdev, memory_module_index, &memory_info))
1691 void rv770_get_max_vddc(struct radeon_device *rdev)
1693 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1696 if (radeon_atom_get_max_vddc(rdev, 0, 0, &vddc))
1702 void rv770_program_response_times(struct radeon_device *rdev)
1709 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time;
1710 backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time;
1721 reference_clock = radeon_get_xclk(rdev);
1728 rv770_write_smc_soft_register(rdev,
1730 rv770_write_smc_soft_register(rdev,
1732 rv770_write_smc_soft_register(rdev,
1734 rv770_write_smc_soft_register(rdev,
1739 rv770_write_smc_soft_register(rdev,
1745 static void rv770_program_dcodt_before_state_switch(struct radeon_device *rdev,
1749 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1770 if ((rdev->family == CHIP_RV730) || (rdev->family == CHIP_RV710))
1771 rv730_program_dcodt(rdev, new_use_dc);
1774 static void rv770_program_dcodt_after_state_switch(struct radeon_device *rdev,
1778 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1799 if ((rdev->family == CHIP_RV730) || (rdev->family == CHIP_RV710))
1800 rv730_program_dcodt(rdev, new_use_dc);
1803 static void rv770_retrieve_odt_values(struct radeon_device *rdev)
1805 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1810 if ((rdev->family == CHIP_RV730) || (rdev->family == CHIP_RV710))
1811 rv730_get_odt_values(rdev);
1814 static void rv770_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
1816 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1851 void rv770_enable_auto_throttle_source(struct radeon_device *rdev,
1855 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1860 rv770_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1865 rv770_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1870 static int rv770_set_thermal_temperature_range(struct radeon_device *rdev,
1889 rdev->pm.dpm.thermal.min_temp = low_temp;
1890 rdev->pm.dpm.thermal.max_temp = high_temp;
1895 int rv770_dpm_enable(struct radeon_device *rdev)
1897 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1898 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
1902 rv770_restore_cgcg(rdev);
1904 if (rv770_dpm_enabled(rdev))
1908 rv770_enable_voltage_control(rdev, true);
1909 ret = rv770_construct_vddc_table(rdev);
1917 rv770_retrieve_odt_values(rdev);
1920 ret = rv770_get_mvdd_configuration(rdev);
1927 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS)
1928 rv770_enable_backbias(rdev, true);
1930 rv770_enable_spread_spectrum(rdev, true);
1933 rv770_enable_thermal_protection(rdev, true);
1935 rv770_program_mpll_timing_parameters(rdev);
1936 rv770_setup_bsp(rdev);
1937 rv770_program_git(rdev);
1938 rv770_program_tp(rdev);
1939 rv770_program_tpp(rdev);
1940 rv770_program_sstp(rdev);
1941 rv770_program_engine_speed_parameters(rdev);
1942 rv770_enable_display_gap(rdev);
1943 rv770_program_vc(rdev);
1946 rv770_enable_dynamic_pcie_gen2(rdev, true);
1948 ret = rv770_upload_firmware(rdev);
1953 ret = rv770_init_smc_table(rdev, boot_ps);
1959 rv770_program_response_times(rdev);
1960 r7xx_start_smc(rdev);
1962 if ((rdev->family == CHIP_RV730) || (rdev->family == CHIP_RV710))
1963 rv730_start_dpm(rdev);
1965 rv770_start_dpm(rdev);
1968 rv770_gfx_clock_gating_enable(rdev, true);
1971 rv770_mg_clock_gating_enable(rdev, true);
1973 rv770_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
1978 int rv770_dpm_late_enable(struct radeon_device *rdev)
1982 if (rdev->irq.installed &&
1983 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
1986 ret = rv770_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
1989 rdev->irq.dpm_thermal = true;
1990 radeon_irq_set(rdev);
1991 result = rv770_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
2000 void rv770_dpm_disable(struct radeon_device *rdev)
2002 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2004 if (!rv770_dpm_enabled(rdev))
2007 rv770_clear_vc(rdev);
2010 rv770_enable_thermal_protection(rdev, false);
2012 rv770_enable_spread_spectrum(rdev, false);
2015 rv770_enable_dynamic_pcie_gen2(rdev, false);
2017 if (rdev->irq.installed &&
2018 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
2019 rdev->irq.dpm_thermal = false;
2020 radeon_irq_set(rdev);
2024 rv770_gfx_clock_gating_enable(rdev, false);
2027 rv770_mg_clock_gating_enable(rdev, false);
2029 if ((rdev->family == CHIP_RV730) || (rdev->family == CHIP_RV710))
2030 rv730_stop_dpm(rdev);
2032 rv770_stop_dpm(rdev);
2034 r7xx_stop_smc(rdev);
2035 rv770_reset_smio_status(rdev);
2038 int rv770_dpm_set_power_state(struct radeon_device *rdev)
2040 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2041 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
2042 struct radeon_ps *old_ps = rdev->pm.dpm.current_ps;
2045 ret = rv770_restrict_performance_levels_before_switch(rdev);
2050 rv770_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
2051 ret = rv770_halt_smc(rdev);
2056 ret = rv770_upload_sw_state(rdev, new_ps);
2061 r7xx_program_memory_timing_parameters(rdev, new_ps);
2063 rv770_program_dcodt_before_state_switch(rdev, new_ps, old_ps);
2064 ret = rv770_resume_smc(rdev);
2069 ret = rv770_set_sw_state(rdev);
2075 rv770_program_dcodt_after_state_switch(rdev, new_ps, old_ps);
2076 rv770_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
2082 void rv770_dpm_reset_asic(struct radeon_device *rdev)
2084 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2085 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
2087 rv770_restrict_performance_levels_before_switch(rdev);
2089 rv770_program_dcodt_before_state_switch(rdev, boot_ps, boot_ps);
2090 rv770_set_boot_state(rdev);
2092 rv770_program_dcodt_after_state_switch(rdev, boot_ps, boot_ps);
2096 void rv770_dpm_setup_asic(struct radeon_device *rdev)
2098 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2100 r7xx_read_clock_registers(rdev);
2101 rv770_read_voltage_smio_registers(rdev);
2102 rv770_get_memory_type(rdev);
2104 rv770_get_mclk_odt_threshold(rdev);
2105 rv770_get_pcie_gen2_status(rdev);
2107 rv770_enable_acpi_pm(rdev);
2110 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_ASPM_L0s)
2111 rv770_enable_l0s(rdev);
2112 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_ASPM_L1)
2113 rv770_enable_l1(rdev);
2114 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1)
2115 rv770_enable_pll_sleep_in_l1(rdev);
2119 void rv770_dpm_display_configuration_changed(struct radeon_device *rdev)
2121 rv770_program_display_gap(rdev);
2145 static void rv7xx_parse_pplib_non_clock_info(struct radeon_device *rdev,
2170 rdev->pm.dpm.boot_ps = rps;
2172 rdev->pm.dpm.uvd_ps = rps;
2175 static void rv7xx_parse_pplib_clock_info(struct radeon_device *rdev,
2179 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2180 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2198 if (rdev->family >= CHIP_CEDAR) {
2228 if (rdev->family >= CHIP_CEDAR)
2237 if (rdev->family >= CHIP_BARTS) {
2252 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
2253 pl->mclk = rdev->clock.default_mclk;
2254 pl->sclk = rdev->clock.default_sclk;
2261 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
2262 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
2263 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
2264 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
2268 int rv7xx_parse_power_table(struct radeon_device *rdev)
2270 struct radeon_mode_info *mode_info = &rdev->mode_info;
2286 rdev->pm.dpm.ps = kcalloc(power_info->pplib.ucNumStates,
2289 if (!rdev->pm.dpm.ps)
2306 kfree(rdev->pm.dpm.ps);
2309 rdev->pm.dpm.ps[i].ps_priv = ps;
2310 rv7xx_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
2319 rv7xx_parse_pplib_clock_info(rdev,
2320 &rdev->pm.dpm.ps[i], j,
2325 rdev->pm.dpm.num_ps = power_info->pplib.ucNumStates;
2329 void rv770_get_engine_memory_ss(struct radeon_device *rdev)
2331 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2334 pi->sclk_ss = radeon_atombios_get_asic_ss_info(rdev, &ss,
2336 pi->mclk_ss = radeon_atombios_get_asic_ss_info(rdev, &ss,
2345 int rv770_dpm_init(struct radeon_device *rdev)
2354 rdev->pm.dpm.priv = pi;
2356 rv770_get_max_vddc(rdev);
2362 ret = r600_get_platform_caps(rdev);
2366 ret = rv7xx_parse_power_table(rdev);
2370 if (rdev->pm.dpm.voltage_response_time == 0)
2371 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
2372 if (rdev->pm.dpm.backbias_response_time == 0)
2373 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
2375 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
2391 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 0);
2394 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, 0);
2396 rv770_get_engine_memory_ss(rdev);
2411 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
2418 if (rdev->flags & RADEON_IS_MOBILITY)
2434 void rv770_dpm_print_power_state(struct radeon_device *rdev,
2443 if (rdev->family >= CHIP_CEDAR) {
2464 r600_dpm_print_ps_status(rdev, rps);
2467 void rv770_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
2470 struct radeon_ps *rps = rdev->pm.dpm.current_ps;
2487 if (rdev->family >= CHIP_CEDAR) {
2497 u32 rv770_dpm_get_current_sclk(struct radeon_device *rdev)
2499 struct radeon_ps *rps = rdev->pm.dpm.current_ps;
2519 u32 rv770_dpm_get_current_mclk(struct radeon_device *rdev)
2521 struct radeon_ps *rps = rdev->pm.dpm.current_ps;
2541 void rv770_dpm_fini(struct radeon_device *rdev)
2545 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
2546 kfree(rdev->pm.dpm.ps[i].ps_priv);
2548 kfree(rdev->pm.dpm.ps);
2549 kfree(rdev->pm.dpm.priv);
2552 u32 rv770_dpm_get_sclk(struct radeon_device *rdev, bool low)
2554 struct rv7xx_ps *requested_state = rv770_get_ps(rdev->pm.dpm.requested_ps);
2562 u32 rv770_dpm_get_mclk(struct radeon_device *rdev, bool low)
2564 struct rv7xx_ps *requested_state = rv770_get_ps(rdev->pm.dpm.requested_ps);
2572 bool rv770_dpm_vblank_too_short(struct radeon_device *rdev)
2574 u32 vblank_time = r600_dpm_get_vblank_time(rdev);
2579 if ((rdev->family == CHIP_RV770) &&
2580 !(rdev->flags & RADEON_IS_MOBILITY))