Lines Matching refs:rdev
33 static u32 rv6xx_scale_count_given_unit(struct radeon_device *rdev,
43 static struct rv6xx_power_info *rv6xx_get_pi(struct radeon_device *rdev)
45 struct rv6xx_power_info *pi = rdev->pm.dpm.priv;
50 static void rv6xx_force_pcie_gen1(struct radeon_device *rdev)
63 for (i = 0; i < rdev->usec_timeout; i++) {
74 static void rv6xx_enable_pcie_gen2_support(struct radeon_device *rdev)
87 static void rv6xx_enable_bif_dynamic_pcie_gen2(struct radeon_device *rdev,
100 static void rv6xx_enable_l0s(struct radeon_device *rdev)
109 static void rv6xx_enable_l1(struct radeon_device *rdev)
121 static void rv6xx_enable_pll_sleep_in_l1(struct radeon_device *rdev)
138 static int rv6xx_convert_clock_to_stepping(struct radeon_device *rdev,
144 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
159 static void rv6xx_output_stepping(struct radeon_device *rdev,
162 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
163 u32 ref_clk = rdev->clock.spll.reference_freq;
165 u32 spll_step_count = rv6xx_scale_count_given_unit(rdev,
170 r600_engine_clock_entry_enable(rdev, step_index, true);
171 r600_engine_clock_entry_enable_pulse_skipping(rdev, step_index, false);
174 r600_engine_clock_entry_enable_post_divider(rdev, step_index, false);
179 r600_engine_clock_entry_enable_post_divider(rdev, step_index, true);
180 r600_engine_clock_entry_set_post_divider(rdev, step_index, (hi_len << 4) | lo_len);
186 r600_engine_clock_entry_set_reference_divider(rdev, step_index,
188 r600_engine_clock_entry_set_feedback_divider(rdev, step_index, fb_divider);
189 r600_engine_clock_entry_set_step_time(rdev, step_index, spll_step_count);
193 static struct rv6xx_sclk_stepping rv6xx_next_vco_step(struct radeon_device *rdev,
209 static bool rv6xx_can_step_post_div(struct radeon_device *rdev,
218 static struct rv6xx_sclk_stepping rv6xx_next_post_div_step(struct radeon_device *rdev,
224 while (rv6xx_can_step_post_div(rdev, &next, target))
230 static bool rv6xx_reached_stepping_target(struct radeon_device *rdev,
239 static void rv6xx_generate_steps(struct radeon_device *rdev,
248 rv6xx_convert_clock_to_stepping(rdev, low, &cur);
249 rv6xx_convert_clock_to_stepping(rdev, high, &target);
251 rv6xx_output_stepping(rdev, step_index++, &cur);
261 if (rv6xx_can_step_post_div(rdev, &cur, &target))
262 next = rv6xx_next_post_div_step(rdev, &cur, &target);
264 next = rv6xx_next_vco_step(rdev, &cur, increasing_vco, R600_VCOSTEPPCT_DFLT);
266 if (rv6xx_reached_stepping_target(rdev, &next, &target, increasing_vco)) {
268 rv6xx_next_vco_step(rdev, &target, !increasing_vco, R600_ENDINGVCOSTEPPCT_DFLT);
271 if (!rv6xx_reached_stepping_target(rdev, &tiny, &cur, !increasing_vco))
272 rv6xx_output_stepping(rdev, step_index++, &tiny);
281 rv6xx_output_stepping(rdev, step_index++, &final_vco);
284 rv6xx_output_stepping(rdev, step_index++, &target);
287 rv6xx_output_stepping(rdev, step_index++, &next);
296 static void rv6xx_generate_single_step(struct radeon_device *rdev,
301 rv6xx_convert_clock_to_stepping(rdev, clock, &step);
302 rv6xx_output_stepping(rdev, index, &step);
305 static void rv6xx_invalidate_intermediate_steps_range(struct radeon_device *rdev,
311 r600_engine_clock_entry_enable(rdev, step_index, false);
314 static void rv6xx_set_engine_spread_spectrum_clk_s(struct radeon_device *rdev,
321 static void rv6xx_set_engine_spread_spectrum_clk_v(struct radeon_device *rdev,
328 static void rv6xx_enable_engine_spread_spectrum(struct radeon_device *rdev,
339 static void rv6xx_set_memory_spread_spectrum_clk_s(struct radeon_device *rdev,
345 static void rv6xx_set_memory_spread_spectrum_clk_v(struct radeon_device *rdev,
351 static void rv6xx_enable_memory_spread_spectrum(struct radeon_device *rdev,
360 static void rv6xx_enable_dynamic_spread_spectrum(struct radeon_device *rdev,
369 static void rv6xx_memory_clock_entry_enable_post_divider(struct radeon_device *rdev,
379 static void rv6xx_memory_clock_entry_set_post_divider(struct radeon_device *rdev,
386 static void rv6xx_memory_clock_entry_set_feedback_divider(struct radeon_device *rdev,
393 static void rv6xx_memory_clock_entry_set_reference_divider(struct radeon_device *rdev,
400 static void rv6xx_vid_response_set_brt(struct radeon_device *rdev, u32 rt)
405 static void rv6xx_enable_engine_feedback_and_reference_sync(struct radeon_device *rdev)
417 static u32 rv6xx_scale_count_given_unit(struct radeon_device *rdev,
425 static u32 rv6xx_compute_count_for_delay(struct radeon_device *rdev,
428 u32 ref_clk = rdev->clock.spll.reference_freq;
430 return rv6xx_scale_count_given_unit(rdev, delay_us * (ref_clk / 100), unit);
433 static void rv6xx_calculate_engine_speed_stepping_parameters(struct radeon_device *rdev,
436 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
450 static void rv6xx_calculate_memory_clock_stepping_parameters(struct radeon_device *rdev,
453 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
480 static void rv6xx_calculate_voltage_stepping_parameters(struct radeon_device *rdev,
483 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
548 static void rv6xx_program_engine_spread_spectrum(struct radeon_device *rdev,
551 u32 ref_clk = rdev->clock.spll.reference_freq;
552 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
557 rv6xx_enable_engine_spread_spectrum(rdev, level, false);
560 if (radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, clock, false, ÷rs) == 0) {
564 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
575 rv6xx_set_engine_spread_spectrum_clk_v(rdev, level, clk_v);
576 rv6xx_set_engine_spread_spectrum_clk_s(rdev, level, clk_s);
577 rv6xx_enable_engine_spread_spectrum(rdev, level, true);
583 static void rv6xx_program_sclk_spread_spectrum_parameters_except_lowest_entry(struct radeon_device *rdev)
585 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
587 rv6xx_program_engine_spread_spectrum(rdev,
591 rv6xx_program_engine_spread_spectrum(rdev,
597 static int rv6xx_program_mclk_stepping_entry(struct radeon_device *rdev,
602 if (radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM, clock, false, ÷rs))
606 rv6xx_memory_clock_entry_set_reference_divider(rdev, entry, dividers.ref_div);
607 rv6xx_memory_clock_entry_set_feedback_divider(rdev, entry, dividers.fb_div);
608 rv6xx_memory_clock_entry_set_post_divider(rdev, entry, dividers.post_div);
611 rv6xx_memory_clock_entry_enable_post_divider(rdev, entry, true);
613 rv6xx_memory_clock_entry_enable_post_divider(rdev, entry, false);
618 static void rv6xx_program_mclk_stepping_parameters_except_lowest_entry(struct radeon_device *rdev)
620 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
625 rv6xx_program_mclk_stepping_entry(rdev, i,
630 static void rv6xx_find_memory_clock_with_highest_vco(struct radeon_device *rdev,
636 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
640 if (radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM,
652 static void rv6xx_program_mclk_spread_spectrum_parameters(struct radeon_device *rdev)
654 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
655 u32 ref_clk = rdev->clock.mpll.reference_freq;
660 rv6xx_enable_memory_spread_spectrum(rdev, false);
663 rv6xx_find_memory_clock_with_highest_vco(rdev,
669 rv6xx_find_memory_clock_with_highest_vco(rdev,
675 rv6xx_find_memory_clock_with_highest_vco(rdev,
682 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
693 rv6xx_set_memory_spread_spectrum_clk_v(rdev, clk_v);
694 rv6xx_set_memory_spread_spectrum_clk_s(rdev, clk_s);
695 rv6xx_enable_memory_spread_spectrum(rdev, true);
701 static int rv6xx_program_voltage_stepping_entry(struct radeon_device *rdev,
707 ret = radeon_atom_get_voltage_gpio_settings(rdev, voltage,
713 r600_voltage_control_program_voltages(rdev, entry, set_pins);
718 static void rv6xx_program_voltage_stepping_parameters_except_lowest_entry(struct radeon_device *rdev)
720 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
724 rv6xx_program_voltage_stepping_entry(rdev, i,
729 static void rv6xx_program_backbias_stepping_parameters_except_lowest_entry(struct radeon_device *rdev)
731 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
744 static void rv6xx_program_sclk_spread_spectrum_parameters_lowest_entry(struct radeon_device *rdev)
746 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
748 rv6xx_program_engine_spread_spectrum(rdev,
753 static void rv6xx_program_mclk_stepping_parameters_lowest_entry(struct radeon_device *rdev)
755 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
758 rv6xx_program_mclk_stepping_entry(rdev, 0,
762 static void rv6xx_program_voltage_stepping_parameters_lowest_entry(struct radeon_device *rdev)
764 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
766 rv6xx_program_voltage_stepping_entry(rdev, 0,
771 static void rv6xx_program_backbias_stepping_parameters_lowest_entry(struct radeon_device *rdev)
773 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
781 static u32 calculate_memory_refresh_rate(struct radeon_device *rdev,
794 static void rv6xx_program_memory_timing_parameters(struct radeon_device *rdev)
796 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
808 radeon_atom_set_engine_dram_timings(rdev, high_clock, 0);
817 (POWERMODE0(calculate_memory_refresh_rate(rdev,
819 POWERMODE1(calculate_memory_refresh_rate(rdev,
821 POWERMODE2(calculate_memory_refresh_rate(rdev,
823 POWERMODE3(calculate_memory_refresh_rate(rdev,
828 static void rv6xx_program_mpll_timing_parameters(struct radeon_device *rdev)
830 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
832 r600_set_mpll_lock_time(rdev, R600_MPLLLOCKTIME_DFLT *
834 r600_set_mpll_reset_time(rdev, R600_MPLLRESETTIME_DFLT);
837 static void rv6xx_program_bsp(struct radeon_device *rdev)
839 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
840 u32 ref_clk = rdev->clock.spll.reference_freq;
847 r600_set_bsp(rdev, pi->bsu, pi->bsp);
850 static void rv6xx_program_at(struct radeon_device *rdev)
852 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
854 r600_set_at(rdev,
861 static void rv6xx_program_git(struct radeon_device *rdev)
863 r600_set_git(rdev, R600_GICST_DFLT);
866 static void rv6xx_program_tp(struct radeon_device *rdev)
871 r600_set_tc(rdev, i, r600_utc[i], r600_dtc[i]);
873 r600_select_td(rdev, R600_TD_DFLT);
876 static void rv6xx_program_vc(struct radeon_device *rdev)
878 r600_set_vrc(rdev, R600_VRC_DFLT);
881 static void rv6xx_clear_vc(struct radeon_device *rdev)
883 r600_set_vrc(rdev, 0);
886 static void rv6xx_program_tpp(struct radeon_device *rdev)
888 r600_set_tpu(rdev, R600_TPU_DFLT);
889 r600_set_tpc(rdev, R600_TPC_DFLT);
892 static void rv6xx_program_sstp(struct radeon_device *rdev)
894 r600_set_sstu(rdev, R600_SSTU_DFLT);
895 r600_set_sst(rdev, R600_SST_DFLT);
898 static void rv6xx_program_fcp(struct radeon_device *rdev)
900 r600_set_fctu(rdev, R600_FCTU_DFLT);
901 r600_set_fct(rdev, R600_FCT_DFLT);
904 static void rv6xx_program_vddc3d_parameters(struct radeon_device *rdev)
906 r600_set_vddc3d_oorsu(rdev, R600_VDDC3DOORSU_DFLT);
907 r600_set_vddc3d_oorphc(rdev, R600_VDDC3DOORPHC_DFLT);
908 r600_set_vddc3d_oorsdc(rdev, R600_VDDC3DOORSDC_DFLT);
909 r600_set_ctxcgtt3d_rphc(rdev, R600_CTXCGTT3DRPHC_DFLT);
910 r600_set_ctxcgtt3d_rsdc(rdev, R600_CTXCGTT3DRSDC_DFLT);
913 static void rv6xx_program_voltage_timing_parameters(struct radeon_device *rdev)
917 r600_vid_rt_set_vru(rdev, R600_VRU_DFLT);
919 r600_vid_rt_set_vrt(rdev,
920 rv6xx_compute_count_for_delay(rdev,
921 rdev->pm.dpm.voltage_response_time,
924 rt = rv6xx_compute_count_for_delay(rdev,
925 rdev->pm.dpm.backbias_response_time,
928 rv6xx_vid_response_set_brt(rdev, (rt + 0x1F) >> 5);
931 static void rv6xx_program_engine_speed_parameters(struct radeon_device *rdev)
933 r600_vid_rt_set_ssu(rdev, R600_SPLLSTEPUNIT_DFLT);
934 rv6xx_enable_engine_feedback_and_reference_sync(rdev);
937 static u64 rv6xx_get_master_voltage_mask(struct radeon_device *rdev)
939 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
947 ret = radeon_atom_get_voltage_gpio_settings(rdev,
959 static void rv6xx_program_voltage_gpio_pins(struct radeon_device *rdev)
961 r600_voltage_control_enable_pins(rdev,
962 rv6xx_get_master_voltage_mask(rdev));
965 static void rv6xx_enable_static_voltage_control(struct radeon_device *rdev,
972 radeon_atom_set_voltage(rdev,
976 r600_voltage_control_deactivate_static_control(rdev,
977 rv6xx_get_master_voltage_mask(rdev));
980 static void rv6xx_enable_display_gap(struct radeon_device *rdev, bool enable)
996 static void rv6xx_program_power_level_enter_state(struct radeon_device *rdev)
998 r600_power_level_set_enter_index(rdev, R600_POWER_LEVEL_MEDIUM);
1018 static void rv6xx_calculate_ap(struct radeon_device *rdev,
1021 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1045 static void rv6xx_calculate_stepping_parameters(struct radeon_device *rdev,
1050 rv6xx_calculate_engine_speed_stepping_parameters(rdev, new_state);
1051 rv6xx_calculate_memory_clock_stepping_parameters(rdev, new_state);
1052 rv6xx_calculate_voltage_stepping_parameters(rdev, new_state);
1053 rv6xx_calculate_ap(rdev, new_state);
1056 static void rv6xx_program_stepping_parameters_except_lowest_entry(struct radeon_device *rdev)
1058 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1060 rv6xx_program_mclk_stepping_parameters_except_lowest_entry(rdev);
1062 rv6xx_program_voltage_stepping_parameters_except_lowest_entry(rdev);
1063 rv6xx_program_backbias_stepping_parameters_except_lowest_entry(rdev);
1064 rv6xx_program_sclk_spread_spectrum_parameters_except_lowest_entry(rdev);
1065 rv6xx_program_mclk_spread_spectrum_parameters(rdev);
1066 rv6xx_program_memory_timing_parameters(rdev);
1069 static void rv6xx_program_stepping_parameters_lowest_entry(struct radeon_device *rdev)
1071 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1073 rv6xx_program_mclk_stepping_parameters_lowest_entry(rdev);
1075 rv6xx_program_voltage_stepping_parameters_lowest_entry(rdev);
1076 rv6xx_program_backbias_stepping_parameters_lowest_entry(rdev);
1077 rv6xx_program_sclk_spread_spectrum_parameters_lowest_entry(rdev);
1080 static void rv6xx_program_power_level_low(struct radeon_device *rdev)
1082 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1084 r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_LOW,
1086 r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_LOW,
1088 r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_LOW,
1090 r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_LOW,
1092 r600_power_level_set_pcie_gen2(rdev, R600_POWER_LEVEL_LOW,
1096 static void rv6xx_program_power_level_low_to_lowest_state(struct radeon_device *rdev)
1098 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1100 r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_LOW, 0);
1101 r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_LOW, 0);
1102 r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_LOW, 0);
1104 r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_LOW,
1107 r600_power_level_set_pcie_gen2(rdev, R600_POWER_LEVEL_LOW,
1112 static void rv6xx_program_power_level_medium(struct radeon_device *rdev)
1114 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1116 r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_MEDIUM,
1118 r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_MEDIUM,
1120 r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_MEDIUM,
1122 r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_MEDIUM,
1124 r600_power_level_set_pcie_gen2(rdev, R600_POWER_LEVEL_MEDIUM,
1128 static void rv6xx_program_power_level_medium_for_transition(struct radeon_device *rdev)
1130 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1132 rv6xx_program_mclk_stepping_entry(rdev,
1136 r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_MEDIUM, 1);
1138 r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_MEDIUM,
1140 r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_MEDIUM,
1143 r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_MEDIUM,
1146 rv6xx_enable_engine_spread_spectrum(rdev, R600_POWER_LEVEL_MEDIUM, false);
1148 r600_power_level_set_pcie_gen2(rdev, R600_POWER_LEVEL_MEDIUM,
1152 static void rv6xx_program_power_level_high(struct radeon_device *rdev)
1154 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1156 r600_power_level_set_voltage_index(rdev, R600_POWER_LEVEL_HIGH,
1158 r600_power_level_set_mem_clock_index(rdev, R600_POWER_LEVEL_HIGH,
1160 r600_power_level_set_eng_clock_index(rdev, R600_POWER_LEVEL_HIGH,
1163 r600_power_level_set_watermark_id(rdev, R600_POWER_LEVEL_HIGH,
1166 r600_power_level_set_pcie_gen2(rdev, R600_POWER_LEVEL_HIGH,
1170 static void rv6xx_enable_backbias(struct radeon_device *rdev, bool enable)
1180 static void rv6xx_program_display_gap(struct radeon_device *rdev)
1185 if (rdev->pm.dpm.new_active_crtcs & 1) {
1188 } else if (rdev->pm.dpm.new_active_crtcs & 2) {
1198 static void rv6xx_set_sw_voltage_to_safe(struct radeon_device *rdev,
1209 rv6xx_program_voltage_stepping_entry(rdev, R600_POWER_LEVEL_CTXSW,
1216 static void rv6xx_set_sw_voltage_to_low(struct radeon_device *rdev,
1221 rv6xx_program_voltage_stepping_entry(rdev, R600_POWER_LEVEL_CTXSW,
1228 static void rv6xx_set_safe_backbias(struct radeon_device *rdev,
1242 static void rv6xx_set_safe_pcie_gen2(struct radeon_device *rdev,
1251 rv6xx_force_pcie_gen1(rdev);
1254 static void rv6xx_enable_dynamic_voltage_control(struct radeon_device *rdev,
1263 static void rv6xx_enable_dynamic_backbias_control(struct radeon_device *rdev,
1272 static int rv6xx_step_sw_voltage(struct radeon_device *rdev,
1281 if ((radeon_atom_get_voltage_step(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
1283 (radeon_atom_round_to_true_voltage(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
1285 (radeon_atom_round_to_true_voltage(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
1296 rv6xx_program_voltage_stepping_entry(rdev, R600_POWER_LEVEL_CTXSW,
1298 msleep((rdev->pm.dpm.voltage_response_time + 999) / 1000);
1304 static int rv6xx_step_voltage_if_increasing(struct radeon_device *rdev,
1312 return rv6xx_step_sw_voltage(rdev,
1319 static int rv6xx_step_voltage_if_decreasing(struct radeon_device *rdev,
1327 return rv6xx_step_sw_voltage(rdev,
1334 static void rv6xx_enable_high(struct radeon_device *rdev)
1336 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1340 r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, true);
1343 static void rv6xx_enable_medium(struct radeon_device *rdev)
1345 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1348 r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, true);
1351 static void rv6xx_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
1353 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1388 static void rv6xx_enable_auto_throttle_source(struct radeon_device *rdev,
1392 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1397 rv6xx_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1402 rv6xx_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1408 static void rv6xx_enable_thermal_protection(struct radeon_device *rdev,
1411 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1414 r600_enable_thermal_protection(rdev, enable);
1417 static void rv6xx_generate_transition_stepping(struct radeon_device *rdev,
1423 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1425 rv6xx_generate_steps(rdev,
1431 static void rv6xx_generate_low_step(struct radeon_device *rdev,
1435 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1438 rv6xx_generate_single_step(rdev,
1443 static void rv6xx_invalidate_intermediate_steps(struct radeon_device *rdev)
1445 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1447 rv6xx_invalidate_intermediate_steps_range(rdev, 0,
1451 static void rv6xx_generate_stepping_table(struct radeon_device *rdev,
1455 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1459 rv6xx_generate_steps(rdev,
1464 rv6xx_generate_steps(rdev,
1471 static void rv6xx_enable_spread_spectrum(struct radeon_device *rdev,
1475 rv6xx_enable_dynamic_spread_spectrum(rdev, true);
1477 rv6xx_enable_engine_spread_spectrum(rdev, R600_POWER_LEVEL_LOW, false);
1478 rv6xx_enable_engine_spread_spectrum(rdev, R600_POWER_LEVEL_MEDIUM, false);
1479 rv6xx_enable_engine_spread_spectrum(rdev, R600_POWER_LEVEL_HIGH, false);
1480 rv6xx_enable_dynamic_spread_spectrum(rdev, false);
1481 rv6xx_enable_memory_spread_spectrum(rdev, false);
1485 static void rv6xx_reset_lvtm_data_sync(struct radeon_device *rdev)
1487 if (ASIC_IS_DCE3(rdev))
1493 static void rv6xx_enable_dynamic_pcie_gen2(struct radeon_device *rdev,
1500 rv6xx_enable_bif_dynamic_pcie_gen2(rdev, true);
1501 rv6xx_enable_pcie_gen2_support(rdev);
1502 r600_enable_dynamic_pcie_gen2(rdev, true);
1505 rv6xx_force_pcie_gen1(rdev);
1506 rv6xx_enable_bif_dynamic_pcie_gen2(rdev, false);
1507 r600_enable_dynamic_pcie_gen2(rdev, false);
1511 static void rv6xx_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev,
1525 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
1528 static void rv6xx_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev,
1542 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
1545 int rv6xx_dpm_enable(struct radeon_device *rdev)
1547 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1548 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
1550 if (r600_dynamicpm_enabled(rdev))
1553 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS)
1554 rv6xx_enable_backbias(rdev, true);
1557 rv6xx_enable_spread_spectrum(rdev, true);
1559 rv6xx_program_mpll_timing_parameters(rdev);
1560 rv6xx_program_bsp(rdev);
1561 rv6xx_program_git(rdev);
1562 rv6xx_program_tp(rdev);
1563 rv6xx_program_tpp(rdev);
1564 rv6xx_program_sstp(rdev);
1565 rv6xx_program_fcp(rdev);
1566 rv6xx_program_vddc3d_parameters(rdev);
1567 rv6xx_program_voltage_timing_parameters(rdev);
1568 rv6xx_program_engine_speed_parameters(rdev);
1570 rv6xx_enable_display_gap(rdev, true);
1572 rv6xx_enable_display_gap(rdev, false);
1574 rv6xx_program_power_level_enter_state(rdev);
1576 rv6xx_calculate_stepping_parameters(rdev, boot_ps);
1579 rv6xx_program_voltage_gpio_pins(rdev);
1581 rv6xx_generate_stepping_table(rdev, boot_ps);
1583 rv6xx_program_stepping_parameters_except_lowest_entry(rdev);
1584 rv6xx_program_stepping_parameters_lowest_entry(rdev);
1586 rv6xx_program_power_level_low(rdev);
1587 rv6xx_program_power_level_medium(rdev);
1588 rv6xx_program_power_level_high(rdev);
1589 rv6xx_program_vc(rdev);
1590 rv6xx_program_at(rdev);
1592 r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true);
1593 r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, true);
1594 r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, true);
1596 rv6xx_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
1598 r600_start_dpm(rdev);
1601 rv6xx_enable_static_voltage_control(rdev, boot_ps, false);
1604 rv6xx_enable_dynamic_pcie_gen2(rdev, boot_ps, true);
1607 r600_gfx_clockgating_enable(rdev, true);
1612 void rv6xx_dpm_disable(struct radeon_device *rdev)
1614 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1615 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
1617 if (!r600_dynamicpm_enabled(rdev))
1620 r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true);
1621 r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, true);
1622 rv6xx_enable_display_gap(rdev, false);
1623 rv6xx_clear_vc(rdev);
1624 r600_set_at(rdev, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF);
1627 r600_enable_thermal_protection(rdev, false);
1629 r600_wait_for_power_level(rdev, R600_POWER_LEVEL_LOW);
1630 r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, false);
1631 r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false);
1633 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS)
1634 rv6xx_enable_backbias(rdev, false);
1636 rv6xx_enable_spread_spectrum(rdev, false);
1639 rv6xx_enable_static_voltage_control(rdev, boot_ps, true);
1642 rv6xx_enable_dynamic_pcie_gen2(rdev, boot_ps, false);
1644 if (rdev->irq.installed &&
1645 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
1646 rdev->irq.dpm_thermal = false;
1647 radeon_irq_set(rdev);
1651 r600_gfx_clockgating_enable(rdev, false);
1653 r600_stop_dpm(rdev);
1656 int rv6xx_dpm_set_power_state(struct radeon_device *rdev)
1658 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
1659 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
1660 struct radeon_ps *old_ps = rdev->pm.dpm.current_ps;
1665 rv6xx_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
1667 rv6xx_clear_vc(rdev);
1668 r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true);
1669 r600_set_at(rdev, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF);
1672 r600_enable_thermal_protection(rdev, false);
1674 r600_wait_for_power_level(rdev, R600_POWER_LEVEL_LOW);
1675 r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, false);
1676 r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false);
1678 rv6xx_generate_transition_stepping(rdev, new_ps, old_ps);
1679 rv6xx_program_power_level_medium_for_transition(rdev);
1682 rv6xx_set_sw_voltage_to_safe(rdev, new_ps, old_ps);
1683 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
1684 rv6xx_set_sw_voltage_to_low(rdev, old_ps);
1687 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS)
1688 rv6xx_set_safe_backbias(rdev, new_ps, old_ps);
1691 rv6xx_set_safe_pcie_gen2(rdev, new_ps, old_ps);
1694 rv6xx_enable_dynamic_voltage_control(rdev, false);
1696 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS)
1697 rv6xx_enable_dynamic_backbias_control(rdev, false);
1700 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
1701 rv6xx_step_voltage_if_increasing(rdev, new_ps, old_ps);
1702 msleep((rdev->pm.dpm.voltage_response_time + 999) / 1000);
1705 r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, true);
1706 r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, false);
1707 r600_wait_for_power_level_unequal(rdev, R600_POWER_LEVEL_LOW);
1709 rv6xx_generate_low_step(rdev, new_ps);
1710 rv6xx_invalidate_intermediate_steps(rdev);
1711 rv6xx_calculate_stepping_parameters(rdev, new_ps);
1712 rv6xx_program_stepping_parameters_lowest_entry(rdev);
1713 rv6xx_program_power_level_low_to_lowest_state(rdev);
1715 r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true);
1716 r600_wait_for_power_level(rdev, R600_POWER_LEVEL_LOW);
1717 r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false);
1720 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) {
1721 ret = rv6xx_step_voltage_if_decreasing(rdev, new_ps, old_ps);
1725 rv6xx_enable_dynamic_voltage_control(rdev, true);
1728 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_BACKBIAS)
1729 rv6xx_enable_dynamic_backbias_control(rdev, true);
1732 rv6xx_enable_dynamic_pcie_gen2(rdev, new_ps, true);
1734 rv6xx_reset_lvtm_data_sync(rdev);
1736 rv6xx_generate_stepping_table(rdev, new_ps);
1737 rv6xx_program_stepping_parameters_except_lowest_entry(rdev);
1738 rv6xx_program_power_level_low(rdev);
1739 rv6xx_program_power_level_medium(rdev);
1740 rv6xx_program_power_level_high(rdev);
1741 rv6xx_enable_medium(rdev);
1742 rv6xx_enable_high(rdev);
1745 rv6xx_enable_thermal_protection(rdev, true);
1746 rv6xx_program_vc(rdev);
1747 rv6xx_program_at(rdev);
1749 rv6xx_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
1754 void rv6xx_setup_asic(struct radeon_device *rdev)
1756 r600_enable_acpi_pm(rdev);
1759 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_ASPM_L0s)
1760 rv6xx_enable_l0s(rdev);
1761 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_ASPM_L1)
1762 rv6xx_enable_l1(rdev);
1763 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1)
1764 rv6xx_enable_pll_sleep_in_l1(rdev);
1768 void rv6xx_dpm_display_configuration_changed(struct radeon_device *rdev)
1770 rv6xx_program_display_gap(rdev);
1794 static void rv6xx_parse_pplib_non_clock_info(struct radeon_device *rdev,
1811 rdev->pm.dpm.boot_ps = rps;
1813 rdev->pm.dpm.uvd_ps = rps;
1816 static void rv6xx_parse_pplib_clock_info(struct radeon_device *rdev,
1850 if (radeon_atom_get_max_vddc(rdev, 0, 0, &vddc) == 0)
1856 if ((rdev->family == CHIP_RV610) || (rdev->family == CHIP_RV630)) {
1865 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
1866 pl->mclk = rdev->clock.default_mclk;
1867 pl->sclk = rdev->clock.default_sclk;
1872 static int rv6xx_parse_power_table(struct radeon_device *rdev)
1874 struct radeon_mode_info *mode_info = &rdev->mode_info;
1890 rdev->pm.dpm.ps = kcalloc(power_info->pplib.ucNumStates,
1893 if (!rdev->pm.dpm.ps)
1910 kfree(rdev->pm.dpm.ps);
1913 rdev->pm.dpm.ps[i].ps_priv = ps;
1914 rv6xx_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
1922 rv6xx_parse_pplib_clock_info(rdev,
1923 &rdev->pm.dpm.ps[i], j,
1928 rdev->pm.dpm.num_ps = power_info->pplib.ucNumStates;
1932 int rv6xx_dpm_init(struct radeon_device *rdev)
1942 rdev->pm.dpm.priv = pi;
1944 ret = r600_get_platform_caps(rdev);
1948 ret = rv6xx_parse_power_table(rdev);
1952 if (rdev->pm.dpm.voltage_response_time == 0)
1953 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
1954 if (rdev->pm.dpm.backbias_response_time == 0)
1955 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
1957 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
1964 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM,
1971 if (rdev->family >= CHIP_RV670)
1977 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 0);
1981 pi->sclk_ss = radeon_atombios_get_asic_ss_info(rdev, &ss,
1983 pi->mclk_ss = radeon_atombios_get_asic_ss_info(rdev, &ss,
1997 (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE))
2007 void rv6xx_dpm_print_power_state(struct radeon_device *rdev,
2025 r600_dpm_print_ps_status(rdev, rps);
2028 void rv6xx_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
2031 struct radeon_ps *rps = rdev->pm.dpm.current_ps;
2054 u32 rv6xx_dpm_get_current_sclk(struct radeon_device *rdev)
2056 struct radeon_ps *rps = rdev->pm.dpm.current_ps;
2077 u32 rv6xx_dpm_get_current_mclk(struct radeon_device *rdev)
2079 struct radeon_ps *rps = rdev->pm.dpm.current_ps;
2099 void rv6xx_dpm_fini(struct radeon_device *rdev)
2103 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
2104 kfree(rdev->pm.dpm.ps[i].ps_priv);
2106 kfree(rdev->pm.dpm.ps);
2107 kfree(rdev->pm.dpm.priv);
2110 u32 rv6xx_dpm_get_sclk(struct radeon_device *rdev, bool low)
2112 struct rv6xx_ps *requested_state = rv6xx_get_ps(rdev->pm.dpm.requested_ps);
2120 u32 rv6xx_dpm_get_mclk(struct radeon_device *rdev, bool low)
2122 struct rv6xx_ps *requested_state = rv6xx_get_ps(rdev->pm.dpm.requested_ps);
2130 int rv6xx_dpm_force_performance_level(struct radeon_device *rdev,
2133 struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
2143 rv6xx_clear_vc(rdev);
2144 r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true);
2145 r600_set_at(rdev, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF);
2146 r600_wait_for_power_level(rdev, R600_POWER_LEVEL_LOW);
2147 r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, false);
2148 r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false);
2149 rv6xx_enable_medium(rdev);
2150 rv6xx_enable_high(rdev);
2152 r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, false);
2153 rv6xx_program_vc(rdev);
2154 rv6xx_program_at(rdev);
2156 rdev->pm.dpm.forced_level = level;