Lines Matching defs:radeon_crtc
122 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
123 struct drm_framebuffer *fb = radeon_crtc->base.primary->fb;
124 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
129 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
132 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset,
135 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset,
138 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
140 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
145 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)
153 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
158 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
161 return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) &
327 struct radeon_crtc *radeon_crtc;
332 radeon_crtc = to_radeon_crtc(crtc);
333 if (radeon_crtc->enabled) {
334 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
336 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
345 struct radeon_crtc *radeon_crtc;
350 radeon_crtc = to_radeon_crtc(crtc);
351 if (radeon_crtc->enabled) {
352 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
354 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);