Lines Matching refs:rdev
40 static void rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
42 void rs400_gart_adjust_size(struct radeon_device *rdev)
45 switch (rdev->mc.gtt_size/(1024*1024)) {
56 (unsigned)(rdev->mc.gtt_size >> 20));
59 rdev->mc.gtt_size = 32 * 1024 * 1024;
64 void rs400_gart_tlb_flush(struct radeon_device *rdev)
67 unsigned int timeout = rdev->usec_timeout;
80 int rs400_gart_init(struct radeon_device *rdev)
84 if (rdev->gart.ptr) {
89 switch(rdev->mc.gtt_size / (1024 * 1024)) {
102 r = radeon_gart_init(rdev);
105 rs400_debugfs_pcie_gart_info_init(rdev);
106 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
107 return radeon_gart_table_ram_alloc(rdev);
110 int rs400_gart_enable(struct radeon_device *rdev)
119 switch(rdev->mc.gtt_size / (1024 * 1024)) {
145 if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) {
152 tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16);
153 tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16);
154 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {
164 tmp = (u32)rdev->gart.table_addr & 0xfffff000;
165 tmp |= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4;
178 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {
189 rs400_gart_tlb_flush(rdev);
191 (unsigned)(rdev->mc.gtt_size >> 20),
192 (unsigned long long)rdev->gart.table_addr);
193 rdev->gart.ready = true;
197 void rs400_gart_disable(struct radeon_device *rdev)
207 void rs400_gart_fini(struct radeon_device *rdev)
209 radeon_gart_fini(rdev);
210 rs400_gart_disable(rdev);
211 radeon_gart_table_ram_free(rdev);
233 void rs400_gart_set_page(struct radeon_device *rdev, unsigned i,
236 u32 *gtt = rdev->gart.ptr;
240 int rs400_mc_wait_for_idle(struct radeon_device *rdev)
245 for (i = 0; i < rdev->usec_timeout; i++) {
256 static void rs400_gpu_init(struct radeon_device *rdev)
259 r420_pipes_init(rdev);
260 if (rs400_mc_wait_for_idle(rdev)) {
266 static void rs400_mc_init(struct radeon_device *rdev)
270 rs400_gart_adjust_size(rdev);
271 rdev->mc.igp_sideport_enabled = radeon_combios_sideport_present(rdev);
273 rdev->mc.vram_is_ddr = true;
274 rdev->mc.vram_width = 128;
275 r100_vram_init_sizes(rdev);
277 radeon_vram_location(rdev, &rdev->mc, base);
278 rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1;
279 radeon_gtt_location(rdev, &rdev->mc);
280 radeon_update_bandwidth_info(rdev);
283 uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg)
288 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
292 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
296 void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
300 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
304 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
310 struct radeon_device *rdev = m->private;
319 if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) {
378 static void rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
381 struct dentry *root = rdev->ddev->primary->debugfs_root;
383 debugfs_create_file("rs400_gart_info", 0444, root, rdev,
388 static void rs400_mc_program(struct radeon_device *rdev)
393 r100_mc_stop(rdev, &save);
396 if (rs400_mc_wait_for_idle(rdev))
397 dev_warn(rdev->dev, "rs400: Wait MC idle timeout before updating MC.\n");
399 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
400 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
402 r100_mc_resume(rdev, &save);
405 static int rs400_startup(struct radeon_device *rdev)
409 r100_set_common_regs(rdev);
411 rs400_mc_program(rdev);
413 r300_clock_startup(rdev);
415 rs400_gpu_init(rdev);
416 r100_enable_bm(rdev);
419 r = rs400_gart_enable(rdev);
424 r = radeon_wb_init(rdev);
428 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
430 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
435 if (!rdev->irq.installed) {
436 r = radeon_irq_kms_init(rdev);
441 r100_irq_set(rdev);
442 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
444 r = r100_cp_init(rdev, 1024 * 1024);
446 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
450 r = radeon_ib_pool_init(rdev);
452 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
459 int rs400_resume(struct radeon_device *rdev)
464 rs400_gart_disable(rdev);
466 r300_clock_startup(rdev);
468 rs400_mc_program(rdev);
470 if (radeon_asic_reset(rdev)) {
471 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
476 radeon_combios_asic_init(rdev->ddev);
478 r300_clock_startup(rdev);
480 radeon_surface_init(rdev);
482 rdev->accel_working = true;
483 r = rs400_startup(rdev);
485 rdev->accel_working = false;
490 int rs400_suspend(struct radeon_device *rdev)
492 radeon_pm_suspend(rdev);
493 r100_cp_disable(rdev);
494 radeon_wb_disable(rdev);
495 r100_irq_disable(rdev);
496 rs400_gart_disable(rdev);
500 void rs400_fini(struct radeon_device *rdev)
502 radeon_pm_fini(rdev);
503 r100_cp_fini(rdev);
504 radeon_wb_fini(rdev);
505 radeon_ib_pool_fini(rdev);
506 radeon_gem_fini(rdev);
507 rs400_gart_fini(rdev);
508 radeon_irq_kms_fini(rdev);
509 radeon_fence_driver_fini(rdev);
510 radeon_bo_fini(rdev);
511 radeon_atombios_fini(rdev);
512 kfree(rdev->bios);
513 rdev->bios = NULL;
516 int rs400_init(struct radeon_device *rdev)
521 r100_vga_render_disable(rdev);
523 radeon_scratch_init(rdev);
525 radeon_surface_init(rdev);
528 r100_restore_sanity(rdev);
530 if (!radeon_get_bios(rdev)) {
531 if (ASIC_IS_AVIVO(rdev))
534 if (rdev->is_atom_bios) {
535 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
538 r = radeon_combios_init(rdev);
543 if (radeon_asic_reset(rdev)) {
544 dev_warn(rdev->dev,
550 if (radeon_boot_test_post_card(rdev) == false)
554 radeon_get_clock_info(rdev->ddev);
556 rs400_mc_init(rdev);
558 radeon_fence_driver_init(rdev);
560 r = radeon_bo_init(rdev);
563 r = rs400_gart_init(rdev);
566 r300_set_reg_safe(rdev);
569 radeon_pm_init(rdev);
571 rdev->accel_working = true;
572 r = rs400_startup(rdev);
575 dev_err(rdev->dev, "Disabling GPU acceleration\n");
576 r100_cp_fini(rdev);
577 radeon_wb_fini(rdev);
578 radeon_ib_pool_fini(rdev);
579 rs400_gart_fini(rdev);
580 radeon_irq_kms_fini(rdev);
581 rdev->accel_working = false;