Lines Matching refs:addr
351 * @pe: addr of the page entry
352 * @addr: dst addr to write into pe
354 * @incr: increase next addr by incr bytes
363 uint64_t addr, unsigned count,
366 trace_radeon_vm_set_page(pe, addr, count, incr, flags);
369 uint64_t src = rdev->gart.table_addr + (addr >> 12) * 8;
373 radeon_asic_vm_write_pages(rdev, ib, pe, addr,
377 radeon_asic_vm_set_pages(rdev, ib, pe, addr,
394 uint64_t addr;
405 addr = radeon_bo_gpu_offset(bo);
414 radeon_vm_set_pages(rdev, &ib, addr, 0, entries, 0, 0);
574 vm->page_tables[pt_idx].addr = 0;
590 * @addr: the unmapped addr
596 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr)
601 result = rdev->gart.pages_entry[addr >> RADEON_GPU_PAGE_SHIFT];
675 if (vm->page_tables[pt_idx].addr == pt)
677 vm->page_tables[pt_idx].addr = pt;
726 * @addr: addr those PTEs should point to
734 uint64_t addr, uint32_t flags)
772 radeon_vm_set_pages(rdev, ib, pe_start, addr, count,
780 radeon_vm_set_pages(rdev, ib, pe_start, addr, count,
782 addr += RADEON_GPU_PAGE_SIZE * count;
787 radeon_vm_set_pages(rdev, ib, frag_start, addr, count,
792 addr += RADEON_GPU_PAGE_SIZE * count;
794 radeon_vm_set_pages(rdev, ib, frag_end, addr, count,
823 uint64_t addr;
826 for (addr = start; addr < end; ) {
827 uint64_t pt_idx = addr >> radeon_vm_block_size;
838 if ((addr & ~mask) == (end & ~mask))
839 nptes = end - addr;
841 nptes = RADEON_VM_PTE_COUNT - (addr & mask);
844 pte += (addr & mask) * 8;
861 addr += nptes;
918 uint64_t addr;
948 addr = (u64)mem->start << PAGE_SHIFT;
958 addr += rdev->vm_manager.vram_base_offset;
961 addr = 0;
1012 bo_va->it.last + 1, addr,